URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [execute.c] - Diff between revs 420 and 472

Rev 420	Rev 472
Line 804...	Line 804...
`{`	`{`
`oraddr_t physical_pc;`	`oraddr_t physical_pc;`

`if ((physical_pc = peek_into_itlb (cpu_state.iqueue.insn_addr)))`	`if ((physical_pc = peek_into_itlb (cpu_state.iqueue.insn_addr)))`
`{`	`{`
`disassemble_instr (physical_pc);`	`disassemble_instr (physical_pc, cpu_state.iqueue.insn_addr,`
	`cpu_state.iqueue.insn);`
`}`	`}`
`else`	`else`
`{`	`{`
`PRINTF ("INTERNAL SIMULATOR ERROR: no trace available\n");`	`PRINTF ("Instruction address translation failed: no trace available\n");`
`}`	`}`
`} /* trace_instr () */`	`} /* trace_instr () */`


`/---------------------------------------------------------------------------/`	`/---------------------------------------------------------------------------/`