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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [execute.c] - Diff between revs 420 and 472

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Rev 420 Rev 472
Line 804... Line 804...
{
{
  oraddr_t  physical_pc;
  oraddr_t  physical_pc;
 
 
  if ((physical_pc = peek_into_itlb (cpu_state.iqueue.insn_addr)))
  if ((physical_pc = peek_into_itlb (cpu_state.iqueue.insn_addr)))
    {
    {
      disassemble_instr (physical_pc);
      disassemble_instr (physical_pc, cpu_state.iqueue.insn_addr,
 
                         cpu_state.iqueue.insn);
    }
    }
  else
  else
    {
    {
      PRINTF ("INTERNAL SIMULATOR ERROR: no trace available\n");
      PRINTF ("Instruction address translation failed: no trace available\n");
    }
    }
}       /* trace_instr () */
}       /* trace_instr () */
 
 
 
 
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/

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