URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 124 |
Rev 202 |
Line 478... |
Line 478... |
}
|
}
|
|
|
if (config.sim.exe_log)
|
if (config.sim.exe_log)
|
dump_exe_log ();
|
dump_exe_log ();
|
|
|
|
if (config.sim.exe_bin_insn_log)
|
|
dump_exe_bin_insn_log (current);
|
|
|
} /* analysis() */
|
} /* analysis() */
|
|
|
|
|
#if !(DYNAMIC_EXECUTION)
|
#if !(DYNAMIC_EXECUTION)
|
|
|
Line 701... |
Line 704... |
}
|
}
|
}
|
}
|
} /* dump_exe_log() */
|
} /* dump_exe_log() */
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Outputs binary copy of instruction to a file */
|
|
/*---------------------------------------------------------------------------*/
|
|
void
|
|
dump_exe_bin_insn_log (struct iqueue_entry *current)
|
|
{
|
|
// Do endian swap before spitting out (will be kept in LE on a LE machine)
|
|
// but more useful to see it in big endian format.
|
|
// Should probably host htonl().
|
|
uint32_t insn = (((current->insn & 0xff)<<24) |
|
|
((current->insn & 0xff00)<<8) |
|
|
((current->insn & 0xff0000)>>8) |
|
|
((current->insn & 0xff000000)>>24));
|
|
|
|
//for(i=0;i<4;i++) tmp_insn[i] = eval_direct8 (insn_addr+i, 0, 0);
|
|
|
|
// Dump it into binary log file
|
|
fwrite((void*)&insn, 4, 1, runtime.sim.fexe_bin_insn_log);
|
|
|
|
|
|
} /* dump_exe_bin_insn_log() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Dump registers
|
/*!Dump registers
|
|
|
Supports the CLI 'r' and 't' commands */
|
Supports the CLI 'r' and 't' commands */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.