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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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| Rev 124 |
Rev 202 |
| Line 478... |
Line 478... |
}
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}
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if (config.sim.exe_log)
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if (config.sim.exe_log)
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dump_exe_log ();
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dump_exe_log ();
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if (config.sim.exe_bin_insn_log)
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dump_exe_bin_insn_log (current);
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} /* analysis() */
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} /* analysis() */
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#if !(DYNAMIC_EXECUTION)
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#if !(DYNAMIC_EXECUTION)
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Line 704... |
}
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}
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}
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}
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} /* dump_exe_log() */
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} /* dump_exe_log() */
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/*---------------------------------------------------------------------------*/
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/*!Outputs binary copy of instruction to a file */
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/*---------------------------------------------------------------------------*/
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void
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dump_exe_bin_insn_log (struct iqueue_entry *current)
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{
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// Do endian swap before spitting out (will be kept in LE on a LE machine)
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// but more useful to see it in big endian format.
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// Should probably host htonl().
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uint32_t insn = (((current->insn & 0xff)<<24) |
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((current->insn & 0xff00)<<8) |
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((current->insn & 0xff0000)>>8) |
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((current->insn & 0xff000000)>>24));
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//for(i=0;i<4;i++) tmp_insn[i] = eval_direct8 (insn_addr+i, 0, 0);
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// Dump it into binary log file
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fwrite((void*)&insn, 4, 1, runtime.sim.fexe_bin_insn_log);
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} /* dump_exe_bin_insn_log() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Dump registers
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/*!Dump registers
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Supports the CLI 'r' and 't' commands */
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Supports the CLI 'r' and 't' commands */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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