OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [generate.c] - Diff between revs 96 and 100

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 96 Rev 100
Line 312... Line 312...
  fprintf (fo, "   with Doxygen. */\n");
  fprintf (fo, "   with Doxygen. */\n");
  fprintf (fo, "\n");
  fprintf (fo, "\n");
 
 
  fprintf (fo, "/* This file was automatically generated by generate (see\n");
  fprintf (fo, "/* This file was automatically generated by generate (see\n");
  fprintf (fo, "   cpu/or32/generate.c) */\n\n");
  fprintf (fo, "   cpu/or32/generate.c) */\n\n");
 
  fprintf (fo, "typedef union {\n\tfloat fval;\n\tuint32_t hval;\n} FLOAT;\n\n");
  fprintf (fo, "static void decode_execute (struct iqueue_entry *current)\n{\n");
  fprintf (fo, "static void decode_execute (struct iqueue_entry *current)\n{\n");
  fprintf (fo, "  uint32_t insn = current->insn;\n");
  fprintf (fo, "  uint32_t insn = current->insn;\n");
  out_lines = 5;
  out_lines = 5;
  return 0;
  return 0;
}
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.