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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [generate.c] - Diff between revs 118 and 121

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Rev 118 Rev 121
Line 216... Line 216...
                       'a' + num_ops, 1 << sbit, 'a' + num_ops,
                       'a' + num_ops, 1 << sbit, 'a' + num_ops,
                       0xffffffff << sbit);
                       0xffffffff << sbit);
      if ((opd->type & OPTYPE_REG) && !dis) {
      if ((opd->type & OPTYPE_REG) && !dis) {
        if(!i) {
        if(!i) {
          shift_fprintf (level, fo, "#define SET_PARAM0(val) cpu_state.reg[a] = val\n");
          shift_fprintf (level, fo, "#define SET_PARAM0(val) cpu_state.reg[a] = val\n");
 
          shift_fprintf (level, fo, "#define REG_PARAM0  a\n");
          set_param = 1;
          set_param = 1;
        }
        }
        shift_fprintf (level, fo, "#define PARAM%i cpu_state.reg[%c]\n", num_ops,
        shift_fprintf (level, fo, "#define PARAM%i cpu_state.reg[%c]\n", num_ops,
                      'a' + num_ops);
                      'a' + num_ops);
        if(opd->type & OPTYPE_DST)
        if(opd->type & OPTYPE_DST)
Line 240... Line 241...
  } while (1);
  } while (1);
 
 
  output_function (fo, or32_opcodes[insn_index].function_name, level);
  output_function (fo, or32_opcodes[insn_index].function_name, level);
 
 
  if (set_param)
  if (set_param)
    shift_fprintf (level, fo, "#undef SET_PARAM\n");
    {
 
      shift_fprintf (level, fo, "#undef SET_PARAM0\n");
 
      shift_fprintf (level, fo, "#undef REG_PARAM0\n");
 
    }
 
 
  for (i = 0; i < num_ops; i++)
  for (i = 0; i < num_ops; i++)
    shift_fprintf (level, fo, "#undef PARAM%i\n", i);
    shift_fprintf (level, fo, "#undef PARAM%i\n", i);
 
 
  return dis_op;
  return dis_op;

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