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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 107 and 112

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Rev 107 Rev 112
Line 33... Line 33...
 
 
  temp2 = (orreg_t)PARAM2;
  temp2 = (orreg_t)PARAM2;
  temp3 = (orreg_t)PARAM1;
  temp3 = (orreg_t)PARAM1;
  temp1 = temp2 + temp3;
  temp1 = temp2 + temp3;
  SET_PARAM0(temp1);
  SET_PARAM0(temp1);
  SET_OV_FLAG_FN (temp1);
 
  if (ARITH_SET_FLAG) {
  /* Set overflow if two negative values gave a positive sum, or if two
    if(!temp1)
     positive values gave a negative sum. Otherwise clear it */
      cpu_state.sprs[SPR_SR] |= SPR_SR_F;
  if ((((long int) temp2 <  0) &&
 
       ((long int) temp3 <  0) &&
 
       ((long int) temp1 >= 0)) ||
 
      (((long int) temp2 >= 0) &&
 
       ((long int) temp3 >= 0) &&
 
       ((long int) temp1 <  0)))
 
    {
 
      cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
 
    }
    else
    else
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
    {
 
      cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
  }
  }
 
 
 
  /* Set the carry flag if (as unsigned values) the result is smaller than
 
     either operand (if it smaller than one, it will be smaller than both, so
 
     we need only test one). */
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
 
    {
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
 
    }
  else
  else
 
    {
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
    cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
 
    }
 
 
 
  /* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
 
     is set. */
 
  if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
 
      ((cpu_state.sprs[SPR_SR] & SPR_SR_OV)  == SPR_SR_OV))
 
    {
 
      except_handle (EXCEPT_RANGE, cpu_state.pc);
 
    }
 
 
  temp4 = temp1;
  temp4 = temp1;
  if (temp4 == temp1)
  if (temp4 == temp1)
    or1k_mstats.byteadd++;
    or1k_mstats.byteadd++;
}
}
Line 211... Line 236...
  temp3 = PARAM2;
  temp3 = PARAM2;
  temp2 = PARAM1;
  temp2 = PARAM1;
  if (temp3)
  if (temp3)
    temp1 = temp2 / temp3;
    temp1 = temp2 / temp3;
  else {
  else {
    mtspr (SPR_SR, SPR_SR_CY | mfspr (SPR_SR)); /* Div by zero sets carry */
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;        /* Div by zero sets carry */
    except_handle (EXCEPT_RANGE, cpu_state.pc);
    except_handle (EXCEPT_RANGE, cpu_state.pc);
    return;
    return;
  }
  }
  SET_OV_FLAG_FN (temp1);
  SET_OV_FLAG_FN (temp1);
  SET_PARAM0(temp1);
  SET_PARAM0(temp1);
Line 226... Line 251...
  temp3 = PARAM2;
  temp3 = PARAM2;
  temp2 = PARAM1;
  temp2 = PARAM1;
  if (temp3)
  if (temp3)
    temp1 = temp2 / temp3;
    temp1 = temp2 / temp3;
  else {
  else {
    mtspr (SPR_SR, SPR_SR_CY | mfspr (SPR_SR)); /* Div by zero sets carry */
    cpu_state.sprs[SPR_SR] |= SPR_SR_CY;        /* Div by zero sets carry */
    except_handle(EXCEPT_RANGE, cpu_state.pc);
    except_handle(EXCEPT_RANGE, cpu_state.pc);
    return;
    return;
  }
  }
  SET_OV_FLAG_FN (temp1);
  SET_OV_FLAG_FN (temp1);
  SET_PARAM0(temp1);
  SET_PARAM0(temp1);

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