| Line 551... |
Line 551... |
except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
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}
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}
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INSTRUCTION (l_mac) {
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INSTRUCTION (l_mac) {
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uorreg_t lo, hi;
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uorreg_t lo, hi;
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LONGEST l;
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LONGEST l;
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orreg_t x, y;
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orreg_t x, y, t;
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|
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lo = cpu_state.sprs[SPR_MACLO];
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lo = cpu_state.sprs[SPR_MACLO];
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hi = cpu_state.sprs[SPR_MACHI];
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hi = cpu_state.sprs[SPR_MACHI];
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x = PARAM0;
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x = PARAM0;
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y = PARAM1;
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y = PARAM1;
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/* PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
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/* PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
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|
|
|
/* Compute the temporary as (signed) 32-bits, then sign-extend to 64 when
|
|
adding in. */
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l = (ULONGEST)lo | ((LONGEST)hi << 32);
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l = (ULONGEST)lo | ((LONGEST)hi << 32);
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l += (LONGEST) x * (LONGEST) y;
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t = x * y;
|
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l += (LONGEST) t;
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|
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/* This implementation is very fast - it needs only one cycle for mac. */
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/* This implementation is very fast - it needs only one cycle for mac. */
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lo = ((ULONGEST)l) & 0xFFFFFFFF;
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lo = ((ULONGEST)l) & 0xFFFFFFFF;
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hi = ((LONGEST)l) >> 32;
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hi = ((LONGEST)l) >> 32;
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cpu_state.sprs[SPR_MACLO] = lo;
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cpu_state.sprs[SPR_MACLO] = lo;
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| Line 591... |
Line 595... |
cpu_state.sprs[SPR_MACLO] = lo;
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cpu_state.sprs[SPR_MACLO] = lo;
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cpu_state.sprs[SPR_MACHI] = hi;
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cpu_state.sprs[SPR_MACHI] = hi;
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/* PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
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/* PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
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}
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}
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INSTRUCTION (l_macrc) {
|
INSTRUCTION (l_macrc) {
|
uorreg_t lo, hi;
|
orreg_t lo;
|
LONGEST l;
|
|
/* No need for synchronization here -- all MAC instructions are 1 cycle long. */
|
/* No need for synchronization here -- all MAC instructions are 1 cycle long. */
|
lo = cpu_state.sprs[SPR_MACLO];
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = cpu_state.sprs[SPR_MACHI];
|
|
l = (ULONGEST) lo | ((LONGEST)hi << 32);
|
|
l >>= 28;
|
|
//PRINTF ("<%08x>\n", (unsigned long)l);
|
//PRINTF ("<%08x>\n", (unsigned long)l);
|
SET_PARAM0((orreg_t)l);
|
SET_PARAM0(lo);
|
cpu_state.sprs[SPR_MACLO] = 0;
|
cpu_state.sprs[SPR_MACLO] = 0;
|
cpu_state.sprs[SPR_MACHI] = 0;
|
cpu_state.sprs[SPR_MACHI] = 0;
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}
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}
|
INSTRUCTION (l_cmov) {
|
INSTRUCTION (l_cmov) {
|
SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
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SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
|
