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[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 118 and 121

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Rev 118 Rev 121
Line 465... Line 465...
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
               runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
               cpu_state.pc_delay);
               cpu_state.pc_delay);
  }
  }
}
}
INSTRUCTION (l_jalr) {
INSTRUCTION (l_jalr) {
  cpu_state.pc_delay = PARAM0;
  /* Badly aligned destination or use of link register triggers an exception */
 
  uorreg_t  temp1 = PARAM0;
 
 
 
  if (REG_PARAM0 == LINK_REGNO)
 
    {
 
      except_handle (EXCEPT_ILLEGAL, cpu_state.pc);
 
    }
 
  else if ((temp1 & 0x3) != 0)
 
    {
 
      except_handle (EXCEPT_ALIGN, cpu_state.pc);
 
    }
 
  else
 
    {
 
      cpu_state.pc_delay = temp1;
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
  setsim_reg(LINK_REGNO, cpu_state.pc + 8);
  next_delay_insn = 1;
  next_delay_insn = 1;
}
}
 
}
INSTRUCTION (l_jr) {
INSTRUCTION (l_jr) {
  cpu_state.pc_delay = PARAM0;
  /* Badly aligned destination triggers an exception */
 
  uorreg_t  temp1 = PARAM0;
 
 
 
  if ((temp1 & 0x3) != 0)
 
    {
 
      except_handle (EXCEPT_ALIGN, cpu_state.pc);
 
    }
 
  else
 
    {
 
      cpu_state.pc_delay = temp1;
  next_delay_insn = 1;
  next_delay_insn = 1;
 
 
  if (config.sim.profile)
  if (config.sim.profile)
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
        {
             cpu_state.pc_delay);
          fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n",
 
                   runtime.sim.cycles, cpu_state.pc_delay);
 
        }
 
    }
}
}
INSTRUCTION (l_rfe) {
INSTRUCTION (l_rfe) {
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
  pcnext = cpu_state.sprs[SPR_EPCR_BASE];
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
  mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
}
}

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