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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 122 and 123

Rev 122	Rev 123
Line 650...	Line 650...
`uint32_t x;`	`uint32_t x;`
`x = PARAM1;`	`x = PARAM1;`
`SET_PARAM0((uorreg_t)x);`	`SET_PARAM0((uorreg_t)x);`
`}`	`}`
`INSTRUCTION (l_mtspr) {`	`INSTRUCTION (l_mtspr) {`
`uint16_t regno = PARAM0 + PARAM2;`	`uint16_t regno = PARAM0 \| PARAM2;`
`uorreg_t value = PARAM1;`	`uorreg_t value = PARAM1;`

`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`	`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
`mtspr(regno, value);`	`mtspr(regno, value);`
`else {`	`else {`
`PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");`	`PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");`
`sim_done();`	`sim_done();`
`}`	`}`
`}`	`}`
`INSTRUCTION (l_mfspr) {`	`INSTRUCTION (l_mfspr) {`
`uint16_t regno = PARAM1 + PARAM2;`	`uint16_t regno = PARAM1 \| PARAM2;`
`uorreg_t value = mfspr(regno);`	`uorreg_t value = mfspr(regno);`

`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`	`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
`SET_PARAM0(value);`	`SET_PARAM0(value);`
`else {`	`else {`