| Line 310... |
Line 310... |
INSTRUCTION (l_rfe) {
|
INSTRUCTION (l_rfe) {
|
pcnext = cpu_state.sprs[SPR_EPCR_BASE];
|
pcnext = cpu_state.sprs[SPR_EPCR_BASE];
|
mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
|
mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
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}
|
}
|
INSTRUCTION (l_nop) {
|
INSTRUCTION (l_nop) {
|
oraddr_t stackaddr;
|
|
uint32_t k = PARAM0;
|
uint32_t k = PARAM0;
|
switch (k) {
|
switch (k) {
|
case NOP_NOP:
|
case NOP_NOP:
|
break;
|
break;
|
case NOP_EXIT:
|
case NOP_EXIT:
|
| Line 336... |
Line 335... |
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("****************** counters reset ******************\n");
|
runtime.sim.reset_cycles = runtime.sim.cycles;
|
runtime.sim.reset_cycles = runtime.sim.cycles;
|
runtime.cpu.reset_instructions = runtime.cpu.instructions;
|
runtime.cpu.reset_instructions = runtime.cpu.instructions;
|
break;
|
break;
|
case NOP_PRINTF:
|
|
stackaddr = evalsim_reg(4);
|
|
simprintf(stackaddr, evalsim_reg(3));
|
|
break;
|
|
case NOP_PUTC: /*JPB */
|
case NOP_PUTC: /*JPB */
|
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
|
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
|
fflush( stdout );
|
fflush( stdout );
|
break;
|
break;
|
|
case NOP_GET_TICKS:
|
|
cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
|
|
cpu_state.reg[12] = runtime.sim.cycles >> 32;
|
|
break;
|
|
case NOP_GET_PS:
|
|
cpu_state.reg[11] = config.sim.clkcycle_ps;
|
|
break;
|
case NOP_REPORT:
|
case NOP_REPORT:
|
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
|
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
|
default:
|
default:
|
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
|
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
|
PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
|
PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
|
