URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Diff between revs 143 and 220

Rev 143	Rev 220
Line 548...	Line 548...
`uint32_t k = PARAM0;`	`uint32_t k = PARAM0;`
`switch (k) {`	`switch (k) {`
`case NOP_NOP:`	`case NOP_NOP:`
`break;`	`break;`
`case NOP_EXIT:`	`case NOP_EXIT:`
`PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));`	`PRINTFQ("exit(%"PRIdREG")\n", evalsim_reg (3));`
`fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",`	`PRINTFQ("@reset : cycles %lld, insn #%lld\n",`
`runtime.sim.reset_cycles, runtime.cpu.reset_instructions);`	`runtime.sim.reset_cycles, runtime.cpu.reset_instructions);`
`fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,`	`PRINTFQ("@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,`
`runtime.cpu.instructions);`	`runtime.cpu.instructions);`
`fprintf(stderr, " diff : cycles %lld, insn #%lld\n",`	`PRINTFQ(" diff : cycles %lld, insn #%lld\n",`
`runtime.sim.cycles - runtime.sim.reset_cycles,`	`runtime.sim.cycles - runtime.sim.reset_cycles,`
`runtime.cpu.instructions - runtime.cpu.reset_instructions);`	`runtime.cpu.instructions - runtime.cpu.reset_instructions);`
`if (config.sim.is_library)`	`if (config.sim.is_library)`
`{`	`{`
`runtime.cpu.halted = 1;`	`runtime.cpu.halted = 1;`