URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [cpu/] [or32/] [or32.c] - Diff between revs 122 and 127

Rev 122	Rev 127
Line 336...	Line 336...
`EF (l_addc), OR32_W_FLAG, it_arith},`	`EF (l_addc), OR32_W_FLAG, it_arith},`
`{"l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK",`	`{"l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK",`
`EF (l_and), OR32_W_FLAG, it_arith},`	`EF (l_and), OR32_W_FLAG, it_arith},`
`{"l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK",`	`{"l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK",`
`EF (l_or), 0, it_arith},`	`EF (l_or), 0, it_arith},`
	`#if HAVE_UNSIGNED_XORI`
	`{"l.xori", "rD,rA,K", "10 0xB DDDDD AAAAA KKKK KKKK KKKK KKKK",`
	`EF (l_xor), 0, it_arith},`
	`#else`
`{"l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII",`	`{"l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII",`
`EF (l_xor), 0, it_arith},`	`EF (l_xor), 0, it_arith},`
	`#endif`
`{"l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII",`	`{"l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII",`
`EF (l_mul), 0, it_arith},`	`EF (l_mul), 0, it_arith},`
`{"l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK",`	`{"l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK",`
`EF (l_mfspr), 0, it_move},`	`EF (l_mfspr), 0, it_move},`
`{"l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL",`	`{"l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL",`