URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [debug/] [jtag.h] - Diff between revs 82 and 98

Rev 82	Rev 98
Line 24...	Line 24...


`#ifndef JTAG__H`	`#ifndef JTAG__H`
`#define JTAG__H`	`#define JTAG__H`

`/! Number of JTAG clock cycles a reset sequence takes /`
`#define JTAG_RESET_CYCLES 5`

`/! Enumeration of the JTAG instruction types /`	`/! Enumeration of the JTAG instruction types /`
`enum jtag_instr {`	`enum jtag_instr {`
`JI_UNDEFINED = -1, /* Won't fit in bitfield */`	`JI_UNDEFINED = -1, /* Won't fit in bitfield */`
`JI_EXTEST = 0x0,`	`JI_EXTEST = 0x0,`
`JI_SAMPLE_PRELOAD = 0x1,`	`JI_SAMPLE_PRELOAD = 0x1,`
Line 84...	Line 81...
`JCB_STALL = 50, /!< Stall the processor /`	`JCB_STALL = 50, /!< Stall the processor /`
`};`	`};`

`/* Function prototypes for external use */`	`/* Function prototypes for external use */`
`extern void jtag_init ();`	`extern void jtag_init ();`
`extern int jtag_reset ();`	`extern void jtag_reset ();`
`extern int jtag_shift_ir (unsigned char *jreg);`	`extern void jtag_shift_ir (unsigned char *jreg,`
`extern int jtag_shift_dr (unsigned char *jreg);`	`int num_bits);`
	`extern void jtag_shift_dr (unsigned char *jreg,`
	`int num_bits);`

`#endif /* JTAG__H */`	`#endif /* JTAG__H */`

`No newline at end of file`	`No newline at end of file`