OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.info] - Diff between revs 429 and 430

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 429 Rev 430
Line 1547... Line 1547...
 
 
`edge_trigger = 0|1'
`edge_trigger = 0|1'
     If 1 (true, the default), the programmable interrupt controller is
     If 1 (true, the default), the programmable interrupt controller is
     edge triggered.  If 0 (false), it is level triggered.
     edge triggered.  If 0 (false), it is level triggered.
 
 
 
          Note: When configured to be edge triggered, interrupts must
 
          be cleared in the PICSR by the processor writing a '0' to the
 
          appropriate bit.
 
 
 
          When configured to be level triggered, the interrupt must be
 
          cleared by lowering the peripheral's IRQ line. Writing '0' to
 
          the PICSR has no effect.
 
 
 
          Peripherals can call the function `report_interrupt' to
 
          signal an interrupt request. When configured for level
 
          triggered interrupts, the function `clear_interrupt' will
 
          clear the appropriate bit in the PICSR. `clear_interrupt' has
 
          no effect when Or1ksim is configured for edge triggered
 
          interrupts - interrupts must be cleared by the processor
 
          writing '0' to the appropriate bit in the PICSR in this case.
 
 
 
 


File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
 
 
3.3.6 Power Management Configuration
3.3.6 Power Management Configuration
Line 4433... Line 4449...
Node: CPU Configuration40280
Node: CPU Configuration40280
Node: Memory Configuration44399
Node: Memory Configuration44399
Node: Memory Management Configuration51121
Node: Memory Management Configuration51121
Node: Cache Configuration53498
Node: Cache Configuration53498
Node: Interrupt Configuration55884
Node: Interrupt Configuration55884
Node: Power Management Configuration56620
Node: Power Management Configuration57446
Node: Branch Prediction Configuration57897
Node: Branch Prediction Configuration58723
Node: Debug Interface Configuration59257
Node: Debug Interface Configuration60083
Node: Peripheral Configuration61600
Node: Peripheral Configuration62426
Node: Memory Controller Configuration62226
Node: Memory Controller Configuration63052
Node: UART Configuration66006
Node: UART Configuration66832
Node: DMA Configuration69525
Node: DMA Configuration70351
Node: Ethernet Configuration71392
Node: Ethernet Configuration72218
Node: GPIO Configuration75474
Node: GPIO Configuration76300
Node: Display Interface Configuration77107
Node: Display Interface Configuration77933
Node: Frame Buffer Configuration79416
Node: Frame Buffer Configuration80242
Node: Keyboard Configuration81280
Node: Keyboard Configuration82106
Node: Disc Interface Configuration83518
Node: Disc Interface Configuration84344
Node: Generic Peripheral Configuration88622
Node: Generic Peripheral Configuration89448
Node: Interactive Command Line90917
Node: Interactive Command Line91743
Node: Verification API97891
Node: Verification API98717
Node: Code Internals102321
Node: Code Internals103147
Node: Coding Conventions102904
Node: Coding Conventions103730
Node: Global Data Structures107331
Node: Global Data Structures108157
Node: Concepts109988
Node: Concepts110814
Ref: Output Redirection110133
Ref: Output Redirection110959
Node: Internal Debugging110672
Node: Internal Debugging111498
Node: Regression Testing111196
Node: Regression Testing112022
Node: GNU Free Documentation License114985
Node: GNU Free Documentation License115811
Node: Index137392
Node: Index138218


End Tag Table
End Tag Table

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.