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Line 1439... Line 1439...
* Cache Configuration::
* Cache Configuration::
* Interrupt Configuration::
* Interrupt Configuration::
* Power Management Configuration::
* Power Management Configuration::
* Branch Prediction Configuration::
* Branch Prediction Configuration::
* Debug Interface Configuration::
* Debug Interface Configuration::
 
* Performance Counters Configuration::
 
 


File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
 
 
3.3.1 CPU Configuration
3.3.1 CPU Configuration
Line 1470... Line 1471...
 
 
        * Data cache present (0x00000002)
        * Data cache present (0x00000002)
 
 
        * Instruction cache present (0x00000004)
        * Instruction cache present (0x00000004)
 
 
        * Data MMY present (0x00000008)
        * Data MMU present (0x00000008)
 
 
        * Instruction MMU present (0x00000010)
        * Instruction MMU present (0x00000010)
 
 
        * Debug unit present (0x00000040)
        * Debug unit present (0x00000040)
 
 
Line 1958... Line 1959...
     Set the number of cycles a branch prediction miss costs.  Default
     Set the number of cycles a branch prediction miss costs.  Default
     value 0.
     value 0.
 
 
 
 


File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
File: or1ksim.info,  Node: Debug Interface Configuration,  Next: Performance Counters Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
 
 
3.3.8 Debug Interface Configuration
3.3.8 Debug Interface Configuration
-----------------------------------
-----------------------------------
 
 
The debug unit and debug interface configuration is described in
The debug unit and debug interface configuration is described in
Line 2011... Line 2012...
     enabled.  This is the only functionality associated with VAPI for
     enabled.  This is the only functionality associated with VAPI for
     the debug unit.  No VAPI commands are sent, nor requests handled.
     the debug unit.  No VAPI commands are sent, nor requests handled.
 
 
 
 


 
File: or1ksim.info,  Node: Performance Counters Configuration,  Prev: Debug Interface Configuration,  Up: Core OpenRISC Configuration
 
 
 
3.3.9 Performance Counters Configuration
 
----------------------------------------
 
 
 
The performance counters unit is described in `section pcu'.  This
 
section may appear at most once.  The following parameters may be
 
specified.
 
 
 
`enabled = 0|1'
 
     If 1 (true), the performance counters unit is enabled.  If 0 (the
 
     default), it is disabled.
 
 
 
 
 

File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
 
 
3.4 Configuring Memory Mapped Peripherals
3.4 Configuring Memory Mapped Peripherals
=========================================
=========================================
 
 
Line 4143... Line 4159...
                                                              (line   6)
                                                              (line   6)
* configuring the keyboard interface:    Keyboard Configuration.
* configuring the keyboard interface:    Keyboard Configuration.
                                                              (line   6)
                                                              (line   6)
* configuring the memory controller:     Memory Controller Configuration.
* configuring the memory controller:     Memory Controller Configuration.
                                                              (line   6)
                                                              (line   6)
 
* configuring the performance counters unit: Performance Counters Configuration.
 
                                                              (line   6)
* configuring the processor:             CPU Configuration.   (line   6)
* configuring the processor:             CPU Configuration.   (line   6)
* configuring the PS2 interface:         Keyboard Configuration.
* configuring the PS2 interface:         Keyboard Configuration.
                                                              (line   6)
                                                              (line   6)
* configuring the UART:                  UART Configuration.  (line   6)
* configuring the UART:                  UART Configuration.  (line   6)
* configuring the Verification API (VAPI): Verification API Configuration.
* configuring the Verification API (VAPI): Verification API Configuration.
Line 4252... Line 4270...
                                                              (line  32)
                                                              (line  32)
* enabled (memory controller configuration): Memory Controller Configuration.
* enabled (memory controller configuration): Memory Controller Configuration.
                                                              (line  44)
                                                              (line  44)
* enabled (MMU configuration):           Memory Management Configuration.
* enabled (MMU configuration):           Memory Management Configuration.
                                                              (line  12)
                                                              (line  12)
 
* enabled (performance counters unit configuration): Performance Counters Configuration.
 
                                                              (line  11)
* enabled (power management configuration): Power Management Configuration.
* enabled (power management configuration): Power Management Configuration.
                                                              (line  35)
                                                              (line  35)
* enabled (UART configuration):          UART Configuration.  (line  18)
* enabled (UART configuration):          UART Configuration.  (line  18)
* enabled (verification API configuration): Verification API Configuration.
* enabled (verification API configuration): Verification API Configuration.
                                                              (line  15)
                                                              (line  15)
Line 4505... Line 4525...
                                                              (line  51)
                                                              (line  51)
* pattern (memory configuration):        Memory Configuration.
* pattern (memory configuration):        Memory Configuration.
                                                              (line  82)
                                                              (line  82)
* pc (Interactive CLI):                  Interactive Command Line.
* pc (Interactive CLI):                  Interactive Command Line.
                                                              (line  51)
                                                              (line  51)
 
* performance counters unit configuration: Performance Counters Configuration.
 
                                                              (line   6)
* persistent TAP device creation:        Setting Up a Persistent TAP device.
* persistent TAP device creation:        Setting Up a Persistent TAP device.
                                                              (line   6)
                                                              (line   6)
* phy_addr:                              Ethernet Configuration.
* phy_addr:                              Ethernet Configuration.
                                                              (line  99)
                                                              (line  99)
* PIC configuration:                     Interrupt Configuration.
* PIC configuration:                     Interrupt Configuration.
Line 4669... Line 4691...
                                                              (line   6)
                                                              (line   6)
* section mc:                            Memory Controller Configuration.
* section mc:                            Memory Controller Configuration.
                                                              (line   6)
                                                              (line   6)
* section memory:                        Memory Configuration.
* section memory:                        Memory Configuration.
                                                              (line   6)
                                                              (line   6)
 
* section pcu:                           Performance Counters Configuration.
 
                                                              (line   6)
* section pic:                           Interrupt Configuration.
* section pic:                           Interrupt Configuration.
                                                              (line   6)
                                                              (line   6)
* section pmu:                           Power Management Configuration.
* section pmu:                           Power Management Configuration.
                                                              (line   6)
                                                              (line   6)
* section sim:                           Simulator Behavior.  (line   6)
* section sim:                           Simulator Behavior.  (line   6)
Line 4863... Line 4887...
Node: Simulator Configuration42971
Node: Simulator Configuration42971
Node: Simulator Behavior43262
Node: Simulator Behavior43262
Node: Verification API Configuration47843
Node: Verification API Configuration47843
Node: CUC Configuration49783
Node: CUC Configuration49783
Node: Core OpenRISC Configuration51775
Node: Core OpenRISC Configuration51775
Node: CPU Configuration52277
Node: CPU Configuration52316
Node: Memory Configuration56396
Node: Memory Configuration56435
Node: Memory Management Configuration63118
Node: Memory Management Configuration63157
Node: Cache Configuration65495
Node: Cache Configuration65534
Node: Interrupt Configuration67881
Node: Interrupt Configuration67920
Node: Power Management Configuration69714
Node: Power Management Configuration69753
Node: Branch Prediction Configuration70991
Node: Branch Prediction Configuration71030
Node: Debug Interface Configuration72351
Node: Debug Interface Configuration72390
Node: Peripheral Configuration74694
Node: Performance Counters Configuration74776
Node: Memory Controller Configuration75320
Node: Peripheral Configuration75261
Node: UART Configuration79100
Node: Memory Controller Configuration75887
Node: DMA Configuration82619
Node: UART Configuration79667
Node: Ethernet Configuration84486
Node: DMA Configuration83186
Node: GPIO Configuration89765
Node: Ethernet Configuration85053
Node: Display Interface Configuration91398
Node: GPIO Configuration90332
Node: Frame Buffer Configuration93707
Node: Display Interface Configuration91965
Node: Keyboard Configuration95571
Node: Frame Buffer Configuration94274
Node: Disc Interface Configuration97809
Node: Keyboard Configuration96138
Node: Generic Peripheral Configuration102913
Node: Disc Interface Configuration98376
Node: Interactive Command Line105208
Node: Generic Peripheral Configuration103480
Node: Verification API112182
Node: Interactive Command Line105775
Node: Code Internals116612
Node: Verification API112749
Node: Coding Conventions117195
Node: Code Internals117179
Node: Global Data Structures121622
Node: Coding Conventions117762
Node: Concepts124279
Node: Global Data Structures122189
Ref: Output Redirection124424
Node: Concepts124846
Ref: Interrupts Internal124962
Ref: Output Redirection124991
Node: Internal Debugging126115
Ref: Interrupts Internal125529
Node: Regression Testing126639
Node: Internal Debugging126682
Node: GNU Free Documentation License130428
Node: Regression Testing127206
Node: Index152835
Node: GNU Free Documentation License130995
 
Node: Index153402


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