OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [doc/] [or1ksim.texi] - Diff between revs 346 and 385

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 346 Rev 385
Line 109... Line 109...
to GNU @command{configure} scripts.  Use @kbd{configure --help} to see
to GNU @command{configure} scripts.  Use @kbd{configure --help} to see
all the options.  The most useful is @code{--prefix} to specify a
all the options.  The most useful is @code{--prefix} to specify a
directory for installation of the tools.
directory for installation of the tools.
 
 
For testing (using @command{make check}), the @code{--target} parameter
For testing (using @command{make check}), the @code{--target} parameter
@emph{must} be specified, to allow the target tool chain to be
may be specified, to allow the target tool chain to be selected.  If not
selected.  If the tools have been installed using the standard OpenRISC
specified, it will default to @code{or32-elf}, which is the same prefix
script, then this should be set to @code{or32-elf}.
used with the standard OpenRISC toolchain installation script.
 
 
A number of @value{OR1KSIM} specific features in the simulator do
A number of @value{OR1KSIM} specific features in the simulator do
require enabling at configuration.  These include
require enabling at configuration.  These include
 
 
@table @code
@table @code
Line 360... Line 360...
@cindex command line for @value{OR1KSIM} standalone use
@cindex command line for @value{OR1KSIM} standalone use
 
 
The general form the standalone command is:
The general form the standalone command is:
 
 
@example
@example
or32-uclinux-sim [-vhiqV] [-f @var{file}] [--nosrv] [--srv=[@var{n}]]
or32-uclinux-sim [-vhiqVt] [-f @var{file}] [--nosrv] [--srv=[@var{n}]]
                 [-m <n>][-d @var{str}]
                 [-m <n>][-d @var{str}]
                 [--enable-profile] [--enable-mprofile] [@var{file}]
                 [--enable-profile] [--enable-mprofile] [@var{file}]
@end example
@end example
 
 
Many of the options have both a short and a long form.  For example
Many of the options have both a short and a long form.  For example
Line 403... Line 403...
@cindex @code{-V}
@cindex @code{-V}
@cindex @code{--verbose}
@cindex @code{--verbose}
Generate extra output messages (equivalent of specifying the ``verbose''
Generate extra output messages (equivalent of specifying the ``verbose''
option in the simulator configuration section (see @pxref{Simulator Behavior, , Simulator Behavior}).
option in the simulator configuration section (see @pxref{Simulator Behavior, , Simulator Behavior}).
 
 
 
@item -t
 
@itemx --trace
 
@cindex @code{-V}
 
@cindex @code{--verbose}
 
Dump previous instruction, next instruction, GPRs and flag after each
 
instruction.
 
 
@item -f @var{file}
@item -f @var{file}
@itemx --file @var{file}
@itemx --file=@var{file}
@cindex @code{-f}
@cindex @code{-f}
@cindex @code{--file}
@cindex @code{--file}
Read configuration commands from the specified file, looking first in
Read configuration commands from the specified file, looking first in
the current directory, and otherwise in the @file{$HOME/.or1k}
the current directory, and otherwise in the @file{$HOME/.or1k}
directory.  If this argument is not specified, the file @file{sim.cfg}
directory.  If this argument is not specified, the file @file{sim.cfg}
Line 434... Line 441...
server, otherwise a random value from the private port range
server, otherwise a random value from the private port range
(41920-65535) will be used.  This option may not be specified with
(41920-65535) will be used.  This option may not be specified with
@code{--nosrv}.  If it is, a rude message is printed and the
@code{--nosrv}.  If it is, a rude message is printed and the
@code{--nosrv} option is ignored.
@code{--nosrv} option is ignored.
 
 
@item -m=@var{size}
@item -m @var{size}
@itemx --memory=@var{size}
@itemx --memory=@var{size}
@cindex @code{-m}
@cindex @code{-m}
@cindex @code{--memory}
@cindex @code{--memory}
Configure a memory block of @var{size} bytes, starting at address
Configure a memory block of @var{size} bytes, starting at address
zero.  The size may be followed by @samp{k}, @samp{K}, @samp{m},
zero.  The size may be followed by @samp{k}, @samp{K}, @samp{m},
Line 453... Line 460...
parameters taking their default value.
parameters taking their default value.
 
 
If a configuration file is also used, it should be sure not to specify
If a configuration file is also used, it should be sure not to specify
an overlapping memory block.
an overlapping memory block.
 
 
@item -d=@var{config_string}
@item -d @var{config_string}
@itemx --debug-config=@var{config_string}
@itemx --debug-config=@var{config_string}
@cindex @code{-d}
@cindex @code{-d}
@cindex @code{--debug-config}
@cindex @code{--debug-config}
Enable selected debug messages in @value{OR1KSIM}.  This parameter is
Enable selected debug messages in @value{OR1KSIM}.  This parameter is
for use by developers only, and is not covered further here.  See the
for use by developers only, and is not covered further here.  See the
Line 825... Line 832...
@end quotation
@end quotation
 
 
@end deftypefn
@end deftypefn
 
 
@deftypefn {@file{or1ksim.h}} int or1ksim_write_mem (unsigned
@deftypefn {@file{or1ksim.h}} int or1ksim_write_mem (unsigned
long int @var{addr}, unsigned char *@var{buf}, int @var{len})
long int @var{addr}, const unsigned char *@var{buf}, int @var{len})
 
 
Write @var{len} bytes to @var{addr}, taking the data from @var{buf}.
Write @var{len} bytes to @var{addr}, taking the data from @var{buf}.
Return @var{len} on success and 0 on failure.
Return @var{len} on success and 0 on failure.
 
 
@quotation Note
@quotation Note
Line 1522... Line 1529...
section may appear multiple times, specifying multiple blocks of
section may appear multiple times, specifying multiple blocks of
memory.
memory.
 
 
@quotation Caution
@quotation Caution
The user may choose whether or not to enable a memory controller.  If a
The user may choose whether or not to enable a memory controller.  If a
memory controller is enabled, then the standard OpenRISC C libraries
memory controller is enabled, then appropriate initalization code must
will initialize it to expect 64MB memory blocks, and any memory
be provided.  The section describing memory controller configuration
declarations @emph{must} reflect this.  The section describing memory
describes the steps necessary for using smaller or larger memory
controller configuration describes the steps necessary for using smaller
sections (@pxref{Memory Controller Configuration, , Memory Controller
or larger memory sections (@pxref{Memory Controller Configuration, ,
Configuration}).
Memory Controller Configuration}).
 
 
The @dfn{uClibc} startup code initalizes a memory controller, assumed to
If a memory controller is @emph{not} enabled, then the standard C
be mapped at 0x93000000.  If a memory controller is @emph{not} enabled,
library code will generate memory access errors.  The solution is to
then the standard C library code will generate memory access errors.
declare an additional writable memory block, mimicing the memory
The solution is to declare an additional writable memory block, mimicing
controller's register bank as follows.
the memory controller's register bank as follows.
 
 
@example
@example
section memory
section memory
  pattern = 0x00
  pattern = 0x00
  type = unknown
  type = unknown
Line 2091... Line 2098...
 
 
The memory controller configuration is described in @code{@w{section
The memory controller configuration is described in @code{@w{section
mc}}.  This section may appear multiple times, specifying multiple
mc}}.  This section may appear multiple times, specifying multiple
memory controllers.
memory controllers.
 
 
 
@quotation Warning
 
There are known to be problems with the current memory controller, which
 
currently is not included in the regression test suite. Users are
 
advised not to use the memory controller in the current release.
 
@end quotation
 
 
@quotation Caution
@quotation Caution
The standard OpenRISC C libraries will initialize the memory
There is no initialization code in the standard @dfn{newlib}
controller to expect 64MB memory blocks, and any memory declarations
library.
@emph{must} reflect this.
 
 
The standard @dfn{uClibc} library assumes a memory controller
 
mapped at 0x93000000 and will initialize the memory controller to expect
 
64MB memory blocks, and any memory declarations @emph{must} reflect
 
this.
 
 
If smaller memory blocks are declared with a memory controller, then
If smaller memory blocks are declared with a memory controller, then
sufficient memory will not be allocated by @value{OR1KSIM}, but out of
sufficient memory will not be allocated by @value{OR1KSIM}, but out of
range memory accesses will not be trapped.  For example declaring a
range memory accesses will not be trapped.  For example declaring a
memory section from 0-4MB with a memory controller enabled would mean
memory section from 0-4MB with a memory controller enabled would mean
Line 2686... Line 2703...
the document @cite{ATA/ATAPI-5 Core Specification} by Richard
the document @cite{ATA/ATAPI-5 Core Specification} by Richard
Herveille, which can be found in the @file{doc} subdirectory.  It is a
Herveille, which can be found in the @file{doc} subdirectory.  It is a
memory mapped component, which resides on the main OpenRISC Wishbone
memory mapped component, which resides on the main OpenRISC Wishbone
data bus.
data bus.
 
 
 
@quotation Warning
 
In the current release of Or1ksim, parsing of the ATA section is
 
broken. Users should not configure the disc interface in this release.
 
@end quotation
 
 
ATA/ATAPI configuration is described in @code{@w{section ata}}.  This section
ATA/ATAPI configuration is described in @code{@w{section ata}}.  This section
may appear multiple times, specifying multiple disc controllers.  The
may appear multiple times, specifying multiple disc controllers.  The
following parameters may be specified.
following parameters may be specified.
 
 
@table @code
@table @code

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.