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Line 34... |
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/* Package includes */
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/* Package includes */
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#include "or1ksim.h"
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#include "or1ksim.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "toplevel-support.h"
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#include "toplevel-support.h"
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#include "debug-unit.h"
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#include "sched.h"
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#include "sched.h"
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#include "execute.h"
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#include "execute.h"
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#include "pic.h"
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#include "pic.h"
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#include "jtag.h"
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#include "jtag.h"
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#include "spr-defs.h"
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#include "sprs.h"
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/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
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/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
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#define MAX_GPRS 32 /*!< Maximum GPRs */
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#define MAX_GPRS 32 /*!< Maximum GPRs */
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#define PPC_REGNUM (MAX_GPRS + 0) /*!< Previous PC */
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#define PPC_REGNUM (MAX_GPRS + 0) /*!< Previous PC */
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#define NPC_REGNUM (MAX_GPRS + 1) /*!< Next PC */
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#define NPC_REGNUM (MAX_GPRS + 1) /*!< Next PC */
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Line 237... |
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} /* or1ksim_run () */
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} /* or1ksim_run () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Step the simulator
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This is just a wrapper for the run function, specifying a time
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corresponding to a single cycle. This will in fact mean that a single
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instruction is executed, even if takes more than one cycle to execute.
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@todo What happens if an event is triggered - that may mean multiple
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instructions.
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@return OR1KSIM_RC_OK if we step to completion, OR1KSIM_RC_BRKPT if we hit
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a breakpoint (not clear how this can be set without CLI access) */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_step ()
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{
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return or1ksim_run ((double) config.sim.clkcycle_ps / 1e12);
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} /* or1ksim_step () */
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/*---------------------------------------------------------------------------*/
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/*!Reset the run-time simulation end point
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/*!Reset the run-time simulation end point
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Reset the time for which the simulation should run to the specified duration
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Reset the time for which the simulation should run to the specified duration
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from NOW (i.e. NOT from when the run started).
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from NOW (i.e. NOT from when the run started).
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Line 516... |
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Read a block of memory.
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/*!Read a block of memory.
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@param[out] buf Where to put the data.
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@param[in] addr The address to read from.
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@param[in] addr The address to read from.
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@param[out] buf Where to put the data.
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@param[in] len The number of bytes to read.
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@param[in] len The number of bytes to read.
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@return Number of bytes read, or zero if error. */
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@return Number of bytes read, or zero if error. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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int
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int
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or1ksim_read_mem (unsigned char *buf,
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or1ksim_read_mem (unsigned int addr,
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unsigned int addr,
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unsigned char *buf,
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int len)
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int len)
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{
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{
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int off; /* Offset into the memory */
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int off; /* Offset into the memory */
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/* Fill the buffer with data */
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/* Fill the buffer with data */
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| Line 570... |
Line 553... |
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Write a block of memory.
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/*!Write a block of memory.
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@param[in] buf Where to get the data from.
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@param[in] addr The address to write to.
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@param[in] addr The address to write to.
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@param[in] buf Where to get the data from.
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@param[in] len The number of bytes to write.
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@param[in] len The number of bytes to write.
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@return Number of bytes written, or zero if error. */
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@return Number of bytes written, or zero if error. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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int
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int
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or1ksim_write_mem (unsigned char *buf,
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or1ksim_write_mem (unsigned int addr,
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unsigned int addr,
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unsigned char *buf,
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int len)
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int len)
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{
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{
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int off; /* Offset into the memory */
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int off; /* Offset into the memory */
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/* Write the bytes to memory */
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/* Write the bytes to memory */
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Line 588... |
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} /* or1ksim_write_mem () */
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} /* or1ksim_write_mem () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Read a single register
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/*!Read a SPR
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The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
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@param[in] sprnum The SPR to read.
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(i.e. SPR NPC) and SR (i.e. SPR SR).
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@param[out] sprval_ptr Where to put the data.
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@param[out] buf Where to put the data.
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@return Non-zero (TRUE) on success, zero (FALSE) otherwise. */
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@param[in] regnum The register to read.
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@param[in] len Size of the register in bytes
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@return Size of the register, or zero if error. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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int
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int
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or1ksim_read_reg (unsigned char *buf,
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or1ksim_read_spr (int sprnum,
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int regnum,
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unsigned int *sprval_ptr)
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int len)
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{
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{
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unsigned long int *regbuf = (unsigned long *) buf;
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/* SPR numbers are up to 16 bits long */
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if ((unsigned int) sprnum <= 0xffff)
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if (4 != len)
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{
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{
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return 0; /* Not 32-bit reg */
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*sprval_ptr = (unsigned int) mfspr ((uint16_t) sprnum);
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return 1;
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}
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}
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else
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/* Get the relevant register */
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if (regnum < MAX_GPRS)
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{
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{
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*regbuf = cpu_state.reg[regnum];
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return 0; /* Silent failure */
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}
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}
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else if (PPC_REGNUM == regnum)
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} /* or1skim_read_spr () */
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/*---------------------------------------------------------------------------*/
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/*!Write a SPR
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@param[in] sprnum The SPR to write.
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@param[in] sprval The data to write.
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@return Non-zero (TRUE) on success, zero (FALSE) otherwise. */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_write_spr (int sprnum,
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unsigned int sprval)
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{
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/* SPR numbers are up to 16 bits long */
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if ((unsigned int) sprnum <= 0xffff)
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{
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{
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*regbuf = cpu_state.sprs[SPR_PPC];
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mtspr ((uint16_t) sprnum, sprval);
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return 1;
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}
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}
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else if (NPC_REGNUM == regnum)
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else
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{
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{
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*regbuf = cpu_state.pc;
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return 0; /* Silent failure */
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}
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}
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else if (SR_REGNUM == regnum)
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} /* or1ksim_write_spr () */
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/*---------------------------------------------------------------------------*/
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/*!Read a single register
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The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
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(i.e. SPR NPC) and SR (i.e. SPR SR).
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Map to the corresponding SPR.
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@param[in] regnum The register to read.
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@param[out] regval_ptr Where to put the data.
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@return Non-zero (TRUE) on success, zero (FALSE) otherwise. */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_read_reg (int regnum,
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unsigned int *regval_ptr)
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{
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{
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*regbuf = cpu_state.sprs[SPR_SR];
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/* GPR's */
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if (regnum < MAX_GPRS)
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{
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return or1ksim_read_spr (regnum + SPR_GPR_BASE, regval_ptr);
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}
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}
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else
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/* SPR's or unknown */
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switch (regnum)
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{
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{
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case PPC_REGNUM: return or1ksim_read_spr (SPR_PPC, regval_ptr);
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case NPC_REGNUM: return or1ksim_read_spr (SPR_NPC, regval_ptr);
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case SR_REGNUM: return or1ksim_read_spr (SPR_SR, regval_ptr);
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default:
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/* Silent error response if we don't know the register */
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/* Silent error response if we don't know the register */
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return 0;
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return 0;
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}
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}
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return len;
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} /* or1ksim_read_reg () */
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} /* or1ksim_read_reg () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Write a single register
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/*!Write a single register
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The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
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The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
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(i.e. SPR NPC) and SR (i.e. SPR SR). The register is specified as a
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(i.e. SPR NPC) and SR (i.e. SPR SR).
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sequence of bytes in target endian order.
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Each byte is packed as a pair of hex digits.
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Map to the corresponding SPR
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@param[in] buf Where to get the data from.
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@param[in] regval The register to write.
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@param[in] regnum The register to write.
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@param[in] regnum The register to write.
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@param[in] len Size of the register in bytes
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@return Size of the register, or zero if error. */
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@return Non-zero (TRUE) on success, zero (FALSE) otherwise. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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int
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int
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or1ksim_write_reg (unsigned char *buf,
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or1ksim_write_reg (int regnum,
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int regnum,
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unsigned int regval)
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int len)
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{
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{
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unsigned long int *regbuf = (unsigned long *) buf;
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/* GPR's */
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unsigned long int regval = *regbuf;
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if (4 != len)
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{
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return 0; /* Not 32-bit reg */
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}
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/* Set the relevant register */
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if (regnum < MAX_GPRS)
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if (regnum < MAX_GPRS)
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{
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{
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cpu_state.reg[regnum] =regval;
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return or1ksim_write_spr (regnum + SPR_GPR_BASE, regval);
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}
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else if (PPC_REGNUM == regnum)
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{
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cpu_state.sprs[SPR_PPC] = regval;
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}
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else if (NPC_REGNUM == regnum)
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{
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if (cpu_state.pc != regval)
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{
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cpu_state.pc = regval;
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cpu_state.delay_insn = 0;
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pcnext = regval + 4;
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}
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}
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else if (SR_REGNUM == regnum)
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{
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cpu_state.sprs[SPR_SR] = regval;
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}
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}
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else
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/* SPR's or unknown */
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switch (regnum)
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{
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{
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case PPC_REGNUM: return or1ksim_write_spr (SPR_PPC, regval);
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case NPC_REGNUM: return or1ksim_write_spr (SPR_NPC, regval);
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case SR_REGNUM: return or1ksim_write_spr (SPR_SR, regval);
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default:
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/* Silent error response if we don't know the register */
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/* Silent error response if we don't know the register */
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return 0;
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return 0;
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}
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}
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} /* or1ksim_write_reg () */
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return len;
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} /* or1ksim_write_reg () */
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/*---------------------------------------------------------------------------*/
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/*!Set the simulator stall state.
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@param[in] state The stall state to set. */
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/*---------------------------------------------------------------------------*/
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void
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or1ksim_set_stall_state (int state)
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{
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set_stall_state (state ? 1 : 0);
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} /* or1ksim_set_stall_state () */
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No newline at end of file
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No newline at end of file
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