| Line 101... |
Line 101... |
config.ext.write_up = upw;
|
config.ext.write_up = upw;
|
|
|
print_config (); /* Will go eventually */
|
print_config (); /* Will go eventually */
|
signal (SIGINT, ctrl_c); /* Not sure we want this really */
|
signal (SIGINT, ctrl_c); /* Not sure we want this really */
|
|
|
runtime.sim.hush = 1; /* Not sure if this is needed */
|
|
do_stats = config.cpu.superscalar ||
|
do_stats = config.cpu.superscalar ||
|
config.cpu.dependstats ||
|
config.cpu.dependstats ||
|
config.sim.history ||
|
config.sim.history ||
|
config.sim.exe_log;
|
config.sim.exe_log;
|
|
|
| Line 183... |
Line 182... |
/* This is probably wrong. This is an Or1ksim breakpoint, not a GNU
|
/* This is probably wrong. This is an Or1ksim breakpoint, not a GNU
|
one. */
|
one. */
|
return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
|
return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
|
}
|
}
|
|
|
|
/* If we are tracing, dump after each instruction. */
|
|
if (!runtime.sim.hush)
|
|
{
|
|
dumpreg ();
|
|
}
|
|
|
/* If we were single stepping, stall immediately. */
|
/* If we were single stepping, stall immediately. */
|
if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST)
|
if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST)
|
{
|
{
|
set_stall_state (1);
|
set_stall_state (1);
|
}
|
}
|
| Line 567... |
Line 572... |
|
|
@return Number of bytes written, or zero if error. */
|
@return Number of bytes written, or zero if error. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
int
|
int
|
or1ksim_write_mem (unsigned long int addr,
|
or1ksim_write_mem (unsigned long int addr,
|
unsigned char *buf,
|
const unsigned char *buf,
|
int len)
|
int len)
|
{
|
{
|
int off; /* Offset into the memory */
|
int off; /* Offset into the memory */
|
|
|
/* Write the bytes to memory */
|
/* Write the bytes to memory */
|
