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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [libtoplevel.c] - Diff between revs 420 and 432

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Rev 420 Rev 432
Line 217... Line 217...
                  runtime.sim.ext_int_set &= ~(1 << i); /* Clear req flag */
                  runtime.sim.ext_int_set &= ~(1 << i); /* Clear req flag */
                }
                }
            }
            }
        }
        }
 
 
      /* Clear any interrupts as requested. For edge triggered interrupts this
      /* Clear any interrupts as requested. This only applies to level
         will happen in the same cycle. For level triggered, it must be an
         sensitive interrupts. Edge triggered are cleared by writing to
         explicit call. */
         PICSR. */
      if (0 != runtime.sim.ext_int_clr)
      if (0 != runtime.sim.ext_int_clr)
        {
        {
          for (i = 0; i < num_ints; i++)
          for (i = 0; i < num_ints; i++)
            {
            {
              /* Only clear interrupts that have been explicitly cleared */
              /* Only clear interrupts that have been explicitly cleared */
Line 346... Line 346...
 
 
 
 
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*!Trigger an edge triggered interrupt
/*!Trigger an edge triggered interrupt
 
 
   This function is appropriate for edge triggered interrupts, which are taken
   This function is appropriate for edge triggered interrupts. These are
   and then immediately cleared.
   cleared by writing to the PICSR SPR.
 
 
   @note There is no check that the specified interrupt number is reasonable
   @note There is no check that the specified interrupt number is reasonable
   (i.e. <= 31).
   (i.e. <= 31).
 
 
   @param[in] i  The interrupt number                                        */
   @param[in] i  The interrupt number                                        */
Line 365... Line 365...
               "level triggered interrupts. Ignored\n");
               "level triggered interrupts. Ignored\n");
    }
    }
  else
  else
    {
    {
      runtime.sim.ext_int_set |= 1 << i;        // Better not be > 31!
      runtime.sim.ext_int_set |= 1 << i;        // Better not be > 31!
      runtime.sim.ext_int_clr |= 1 << i;        // Better not be > 31!
 
    }
    }
}       /* or1ksim_interrupt () */
}       /* or1ksim_interrupt () */
 
 
 
 
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/

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