| Line 39... |
Line 39... |
#include "sched.h"
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#include "sched.h"
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#include "execute.h"
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#include "execute.h"
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#include "pic.h"
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#include "pic.h"
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#include "jtag.h"
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#include "jtag.h"
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/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
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#define MAX_GPRS 32 /*!< Maximum GPRs */
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#define PPC_REGNUM (MAX_GPRS + 0) /*!< Previous PC */
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#define NPC_REGNUM (MAX_GPRS + 1) /*!< Next PC */
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#define SR_REGNUM (MAX_GPRS + 2) /*!< Supervision Register */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Initialize the simulator.
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/*!Initialize the simulator.
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Allows specification of an (optional) config file and an image file. Builds
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Allows specification of an (optional) config file and an image file. Builds
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| Line 92... |
Line 98... |
if (parse_args (dummy_argc, dummy_argv))
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if (parse_args (dummy_argc, dummy_argv))
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{
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{
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return OR1KSIM_RC_BADINIT;
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return OR1KSIM_RC_BADINIT;
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}
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}
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config.sim.is_library = 1; /* Library operation */
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config.sim.profile = 0; /* No profiling */
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config.sim.profile = 0; /* No profiling */
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config.sim.mprofile = 0;
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config.sim.mprofile = 0;
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config.ext.class_ptr = class_ptr; /* SystemC linkage */
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config.ext.class_ptr = class_ptr; /* SystemC linkage */
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config.ext.read_up = upr;
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config.ext.read_up = upr;
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| Line 156... |
Line 163... |
or1ksim_run (double duration)
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or1ksim_run (double duration)
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{
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{
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const int num_ints = sizeof (runtime.sim.ext_int_set) * 8;
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const int num_ints = sizeof (runtime.sim.ext_int_set) * 8;
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/* If we are stalled we can't do anything. We treat this as hitting a
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/* If we are stalled we can't do anything. We treat this as hitting a
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breakpoint. */
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breakpoint or halting. */
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if(runtime.cpu.stalled)
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if(runtime.cpu.stalled)
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{
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{
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return OR1KSIM_RC_BRKPT;
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return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
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}
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}
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/* Reset the duration */
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/* Reset the duration */
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or1ksim_reset_duration (duration);
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or1ksim_reset_duration (duration);
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| Line 179... |
Line 186... |
* performed in between. */
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* performed in between. */
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runtime.sim.mem_cycles = 0;
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runtime.sim.mem_cycles = 0;
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if (cpu_clock ())
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if (cpu_clock ())
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{
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{
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return OR1KSIM_RC_BRKPT; /* Hit a breakpoint */
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/* This is probably wrong. This is an Or1ksim breakpoint, not a GNU
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one. */
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return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
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}
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/* If we are stalled we can't do anything. We treat this as hitting a
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breakpoint or halting. */
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if(runtime.cpu.stalled)
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{
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return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
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}
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}
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runtime.sim.cycles += runtime.sim.mem_cycles;
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runtime.sim.cycles += runtime.sim.mem_cycles;
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/* Take any external interrupts. Outer test is for the common case for
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/* Take any external interrupts. Outer test is for the common case for
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| Line 229... |
Line 245... |
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} /* or1ksim_run() */
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} /* or1ksim_run() */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Step the simulator
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This is just a wrapper for the run function, specifying a time
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corresponding to a single cycle. This will in fact mean that a single
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instruction is executed, even if takes more than one cycle to execute.
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@todo What happens if an event is triggered - that may mean multiple
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instructions.
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@return OR1KSIM_RC_OK if we step to completion, OR1KSIM_RC_BRKPT if we hit
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a breakpoint (not clear how this can be set without CLI access) */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_step ()
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{
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return or1ksim_run ((double) config.sim.clkcycle_ps / 1e12);
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} /* or1ksim_step () */
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/*---------------------------------------------------------------------------*/
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/*!Reset the run-time simulation end point
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/*!Reset the run-time simulation end point
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Reset the time for which the simulation should run to the specified duration
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Reset the time for which the simulation should run to the specified duration
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from NOW (i.e. NOT from when the run started).
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from NOW (i.e. NOT from when the run started).
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| Line 504... |
Line 541... |
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return (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
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return (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
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} /* or1ksim_jtag_shift_dr () */
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} /* or1ksim_jtag_shift_dr () */
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No newline at end of file
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/*---------------------------------------------------------------------------*/
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/*!Read a block of memory.
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@param[out] buf Where to put the data.
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@param[in] addr The address to read from.
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@param[in] len The number of bytes to read.
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@return Number of bytes read, or zero if error. */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_read_mem (unsigned char *buf,
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unsigned int addr,
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int len)
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{
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int off; /* Offset into the memory */
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/* Fill the buffer with data */
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for (off = 0; off < len; off++)
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{
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/* Check memory area is valid */
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if (NULL == verify_memoryarea (addr + off))
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{
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/* Fail silently - others can raise any error message. */
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return 0;
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}
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else
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{
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/* Get the memory direct - no translation. */
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buf[off] = eval_direct8 (addr + off, 0, 0);
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}
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}
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return len;
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} /* or1ksim_read_mem () */
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/*---------------------------------------------------------------------------*/
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/*!Write a block of memory.
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@param[in] buf Where to get the data from.
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@param[in] addr The address to write to.
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@param[in] len The number of bytes to write.
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@return Number of bytes written, or zero if error. */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_write_mem (unsigned char *buf,
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unsigned int addr,
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int len)
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{
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int off; /* Offset into the memory */
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/* Write the bytes to memory */
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for (off = 0; off < len; off++)
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{
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if (NULL == verify_memoryarea (addr + off))
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{
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/* Fail silently - others can raise any error message. */
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return 0;
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}
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else
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{
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/* circumvent the read-only check usually done for mem accesses data
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is in host order, because that's what set_direct32 needs */
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set_program8 (addr + off, buf[off]);
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}
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}
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return len;
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} /* or1ksim_write_mem () */
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/*---------------------------------------------------------------------------*/
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/*!Read a single register
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The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
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(i.e. SPR NPC) and SR (i.e. SPR SR).
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@param[out] buf Where to put the data.
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@param[in] regnum The register to read.
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@param[in] len Size of the register in bytes
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@return Size of the register, or zero if error. */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_read_reg (unsigned char *buf,
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int regnum,
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int len)
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{
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unsigned long int *regbuf = (unsigned long *) buf;
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|
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if (4 != len)
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{
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return 0; /* Not 32-bit reg */
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}
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/* Get the relevant register */
|
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if (regnum < MAX_GPRS)
|
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{
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*regbuf = cpu_state.reg[regnum];
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}
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else if (PPC_REGNUM == regnum)
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{
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*regbuf = cpu_state.sprs[SPR_PPC];
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}
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else if (NPC_REGNUM == regnum)
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{
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*regbuf = cpu_state.pc;
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}
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else if (SR_REGNUM == regnum)
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{
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*regbuf = cpu_state.sprs[SPR_SR];
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}
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else
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{
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/* Silent error response if we don't know the register */
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return 0;
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}
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return len;
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} /* or1ksim_read_reg () */
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/*---------------------------------------------------------------------------*/
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/*!Write a single register
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The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
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(i.e. SPR NPC) and SR (i.e. SPR SR). The register is specified as a
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sequence of bytes in target endian order.
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Each byte is packed as a pair of hex digits.
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@param[in] buf Where to get the data from.
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@param[in] regnum The register to write.
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@param[in] len Size of the register in bytes
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@return Size of the register, or zero if error. */
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/*---------------------------------------------------------------------------*/
|
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int
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or1ksim_write_reg (unsigned char *buf,
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int regnum,
|
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int len)
|
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{
|
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unsigned long int *regbuf = (unsigned long *) buf;
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unsigned long int regval = *regbuf;
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|
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if (4 != len)
|
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{
|
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return 0; /* Not 32-bit reg */
|
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}
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|
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/* Set the relevant register */
|
|
if (regnum < MAX_GPRS)
|
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{
|
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cpu_state.reg[regnum] =regval;
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|
}
|
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else if (PPC_REGNUM == regnum)
|
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{
|
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cpu_state.sprs[SPR_PPC] = regval;
|
|
}
|
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else if (NPC_REGNUM == regnum)
|
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{
|
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if (cpu_state.pc != regval)
|
|
{
|
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cpu_state.pc = regval;
|
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cpu_state.delay_insn = 0;
|
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pcnext = regval + 4;
|
|
}
|
|
}
|
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else if (SR_REGNUM == regnum)
|
|
{
|
|
cpu_state.sprs[SPR_SR] = regval;
|
|
}
|
|
else
|
|
{
|
|
/* Silent error response if we don't know the register */
|
|
return 0;
|
|
}
|
|
|
|
return len;
|
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|
|
} /* or1ksim_write_reg () */
|
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No newline at end of file
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