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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [mmu/] [immu.c] - Diff between revs 224 and 556

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Rev 224 Rev 556
Line 37... Line 37...
#include "stats.h"
#include "stats.h"
#include "except.h"
#include "except.h"
#include "spr-dump.h"
#include "spr-dump.h"
#include "misc.h"
#include "misc.h"
#include "sim-cmd.h"
#include "sim-cmd.h"
 
#include "pcu.h"
 
 
 
 
struct immu *immu_state;
struct immu *immu_state;
 
 
/* Insn MMU */
/* Insn MMU */
Line 130... Line 131...
      return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
      return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
    }
    }
 
 
  /* No, we didn't. */
  /* No, we didn't. */
  immu_stats.fetch_tlbmiss++;
  immu_stats.fetch_tlbmiss++;
#if 0
 
  for (i = 0; i < immu->nways; i++)
 
    if (((cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] & SPR_ITLBMR_LRU) >> 6) <
 
        minlru)
 
      minway = i;
 
 
 
  cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] &= ~SPR_ITLBMR_VPN;
 
  cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] |= vpn << 12;
 
  for (i = 0; i < immu->nways; i++)
 
    {
 
      uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE (i) + set];
 
      if (lru & SPR_ITLBMR_LRU)
 
        {
 
          lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
 
          cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] = lru;
 
        }
 
    }
 
  cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] &= ~SPR_ITLBMR_LRU;
 
  cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] |= (immu->nsets - 1) << 6;
 
 
 
  /* 1 to 1 mapping */
 
  cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] &= ~SPR_ITLBTR_PPN;
 
  cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] |= vpn << 12;
 
 
 
  cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] |= SPR_ITLBMR_V;
 
#endif
 
 
 
  /* if tlb refill implemented in HW */
  /* if tlb refill implemented in HW */
  /* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * immu->pagesize + (virtaddr % immu->pagesize); */
  /* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * immu->pagesize + (virtaddr % immu->pagesize); */
  runtime.sim.mem_cycles += immu->missdelay;
  runtime.sim.mem_cycles += immu->missdelay;
 
 
  except_handle (EXCEPT_ITLBMISS, virtaddr);
  except_handle (EXCEPT_ITLBMISS, virtaddr);
 
 
 
  if (config.pcu.enabled)
 
    pcu_count_event(SPR_PCMR_ITLBM);
 
 
  return 0;
  return 0;
}
}
 
 
/* DESC: try to find EA -> PA transaltion without changing
/* DESC: try to find EA -> PA transaltion without changing
 *       any of precessor states. if this is not passible gives up
 *       any of precessor states. if this is not passible gives up

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