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[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [eth.c] - Diff between revs 451 and 457

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Rev 451 Rev 457
Line 69... Line 69...
#ifndef ETH_DEBUG
#ifndef ETH_DEBUG
# define ETH_DEBUG  1
# define ETH_DEBUG  1
#endif
#endif
 
 
/*! Period (clock cycles) for rescheduling Rx and Tx controllers. */
/*! Period (clock cycles) for rescheduling Rx and Tx controllers. */
#define  RTX_RESCHED_PERIOD  1
#define  RTX_RESCHED_PERIOD  10000
 
 
/*! MAC address that is always accepted. */
/*! MAC address that is always accepted. */
static const unsigned char mac_broadcast[ETHER_ADDR_LEN] =
static const unsigned char mac_broadcast[ETHER_ADDR_LEN] =
  { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 
 
Line 1369... Line 1369...
{
{
  struct eth_device *eth = dat;
  struct eth_device *eth = dat;
 
 
#if ETH_DEBUG
#if ETH_DEBUG
  /* Only trace registers of particular interest */
  /* Only trace registers of particular interest */
 
 
  switch (addr)
  switch (addr)
    {
    {
    case ETH_MODER:
    case ETH_MODER:
    case ETH_INT_SOURCE:
    case ETH_INT_SOURCE:
    case ETH_INT_MASK:
    case ETH_INT_MASK:
Line 1383... Line 1384...
    case ETH_COLLCONF:
    case ETH_COLLCONF:
    case ETH_TX_BD_NUM:
    case ETH_TX_BD_NUM:
    case ETH_CTRLMODER:
    case ETH_CTRLMODER:
    case ETH_MAC_ADDR0:
    case ETH_MAC_ADDR0:
    case ETH_MAC_ADDR1:
    case ETH_MAC_ADDR1:
      printf ("eth_write32: %s = 0x%08lx\n", eth_regname (addr),
          printf ("eth_write32: 0x%08lx to %s ", (unsigned long) value,
              (unsigned long int) value);
                  eth_regname (addr));
 
 
 
  }
 
 
 
  /* Detail register transitions on MODER, INT_SOURCE AND INT_MASK */
 
 
 
  switch (addr)
 
  {
 
  case ETH_MODER:
 
          printf("0x%08lx -> ", (unsigned long) eth->regs.moder);
 
          break;
 
  case ETH_INT_SOURCE:
 
          printf("0x%08lx -> ", (unsigned long) eth->regs.int_source);
 
          break;
 
  case ETH_INT_MASK:
 
          printf("0x%08lx -> ", (unsigned long) eth->regs.int_mask);
 
          break;
    }
    }
 
 
 
 
 
 
#endif
#endif
 
 
  switch (addr)
  switch (addr)
    {
    {
    case ETH_MODER:
    case ETH_MODER:
Line 1524... Line 1544...
                   "Warning: eth_write32( 0x%" PRIxADDR " ): Illegal address\n",
                   "Warning: eth_write32( 0x%" PRIxADDR " ): Illegal address\n",
                   addr + eth->baseaddr);
                   addr + eth->baseaddr);
        }
        }
      break;
      break;
    }
    }
 
 
 
#if ETH_DEBUG
 
 
 
  switch (addr)
 
  {
 
  case ETH_MODER:
 
          printf("0x%08lx", (unsigned long) eth->regs.moder);
 
          break;
 
  case ETH_INT_SOURCE:
 
          printf("0x%08lx", (unsigned long) eth->regs.int_source);
 
          break;
 
  case ETH_INT_MASK:
 
          printf("0x%08lx", (unsigned long) eth->regs.int_mask);
 
          break;
 
  case ETH_IPGT:
 
  case ETH_IPGR1:
 
  case ETH_IPGR2:
 
  case ETH_PACKETLEN:
 
  case ETH_COLLCONF:
 
  case ETH_TX_BD_NUM:
 
  case ETH_CTRLMODER:
 
  case ETH_MAC_ADDR0:
 
  case ETH_MAC_ADDR1:
 
          break;
 
  }
 
 
 
  printf("\n");
 
#endif
 
 
 
 
}       /* eth_write32 () */
}       /* eth_write32 () */
 
 
 
 
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*!Enable or disable the Ethernet interface
/*!Enable or disable the Ethernet interface

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