URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [mc-defines.h] - Diff between revs 112 and 385

Rev 112	Rev 385
Line 59...	Line 59...
`#define MC_CSC_MEMTYPE_SDRAM 0`	`#define MC_CSC_MEMTYPE_SDRAM 0`
`#define MC_CSC_MEMTYPE_SSRAM 1`	`#define MC_CSC_MEMTYPE_SSRAM 1`
`#define MC_CSC_MEMTYPE_ASYNC 2`	`#define MC_CSC_MEMTYPE_ASYNC 2`
`#define MC_CSC_MEMTYPE_SYNC 3`	`#define MC_CSC_MEMTYPE_SYNC 3`

	`#define MC_CE_VALID (N_CE - 1)`
`#define MC_CSR_VALID 0xFF000703LU`	`#define MC_CSR_VALID 0xFF000703LU`
`#define MC_POC_VALID 0x0000000FLU`	`#define MC_POC_VALID 0x0000000FLU`
`#define MC_BA_MASK_VALID 0x000003FFLU`	`#define MC_BA_MASK_VALID 0x000003FFLU`
`#define MC_CSC_VALID 0x00FF0FFFLU`	`#define MC_CSC_VALID 0x00FF0FFFLU`
`#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU`	`#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU`