URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [memory.c] - Diff between revs 224 and 418

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Rev 224	Rev 418
Line 61...	Line 61...
`* starting with seed */`	`* starting with seed */`
`enum`	`enum`
`{`	`{`
`MT_UNKNOWN,`	`MT_UNKNOWN,`
`MT_PATTERN,`	`MT_PATTERN,`
`MT_RANDOM`	`MT_RANDOM,`
	`MT_EXITNOPS`
`} type;`	`} type;`
`};`	`};`

`static uint32_t`	`static uint32_t`
`simmem_read32 (oraddr_t addr, void *dat)`	`simmem_read32 (oraddr_t addr, void *dat)`
Line 205...	Line 206...
`for (i = 0; i < mem->size; i++, mem_area++)`	`for (i = 0; i < mem->size; i++, mem_area++)`
`*mem_area = mem->pattern;`	`*mem_area = mem->pattern;`
`break;`	`break;`
`case MT_UNKNOWN:`	`case MT_UNKNOWN:`
`break;`	`break;`
	`case MT_EXITNOPS:`
	`/* Fill memory with OR1K exit NOP */`
	`for (i = 0; i < mem->size; i++, mem_area++)`
	`switch(i & 0x3) {`
	`case 3:`
	`*mem_area = 0x15;`
	`break;`
	`case 0:`
	`*mem_area = 0x01;`
	`break;`
	`default:`
	`*mem_area = 0x00;`
	`break;`
	`}`
	`break;`
`default:`	`default:`
`fprintf (stderr, "Invalid memory configuration type.\n");`	`fprintf (stderr, "Invalid memory configuration type.\n");`
`exit (1);`	`exit (1);`
`}`	`}`
`}`	`}`
Line 273...	Line 289...
`else if (0 == strcasecmp (val.str_val, "zero"))`	`else if (0 == strcasecmp (val.str_val, "zero"))`
`{`	`{`
`mem->type = MT_PATTERN;`	`mem->type = MT_PATTERN;`
`mem->pattern = 0;`	`mem->pattern = 0;`
`}`	`}`
	`else if (0 == strcasecmp (val.str_val, "exitnops"))`
	`{`
	`mem->type = MT_EXITNOPS;`
	`mem->pattern = 0;`
	`}`
`else`	`else`
`{`	`{`
`fprintf (stderr, "Warning: memory type invalid. Ignored");`	`fprintf (stderr, "Warning: memory type invalid. Ignored");`
`}`	`}`
`} /* memory_type() */`	`} /* memory_type() */`

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[/] [openrisc/] [trunk/] [or1ksim/] [peripheral/] [memory.c] - Diff between revs 224 and 418