| Line 97... |
Line 97... |
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
|
except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
|
except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
|
return;
|
return;
|
}
|
}
|
|
|
if (cpu_state.pic_lines & lmask)
|
if (cpu_state.sprs[SPR_PICSR] & lmask)
|
{
|
{
|
/* No edge occured, warn about performance penalty and exit */
|
/* Interrupt already signaled and pending */
|
fprintf (stderr, "Warning: Int line %d did not change state\n", line);
|
fprintf (stderr, "Warning: Int line %d did not change state\n", line);
|
return;
|
return;
|
}
|
}
|
|
|
cpu_state.pic_lines |= lmask;
|
|
cpu_state.sprs[SPR_PICSR] |= lmask;
|
cpu_state.sprs[SPR_PICSR] |= lmask;
|
|
|
if ((cpu_state.sprs[SPR_PICMR] & lmask) || line < 2)
|
if ((cpu_state.sprs[SPR_PICMR] & lmask) || line < 2)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
|
SCHED_ADD (pic_rep_int, NULL, 0);
|
SCHED_ADD (pic_rep_int, NULL, 0);
|
| Line 116... |
Line 115... |
|
|
/* Clears an int on a pic line */
|
/* Clears an int on a pic line */
|
void
|
void
|
clear_interrupt (int line)
|
clear_interrupt (int line)
|
{
|
{
|
cpu_state.pic_lines &= ~(1 << line);
|
/* When level triggered, clear corresponding bit in PICSR */
|
|
|
if (!config.pic.edge_trigger)
|
if (!config.pic.edge_trigger)
|
|
{
|
cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
|
cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
|
}
|
}
|
|
}
|
|
|
/*----------------------------------------------------[ PIC configuration ]---*/
|
/*----------------------------------------------------[ PIC configuration ]---*/
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
