URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [sim-cmd.c] - Diff between revs 240 and 494
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 240 |
Rev 494 |
| Line 1... |
Line 1... |
/* sim-cmd.c -- Simulator command parsing
|
/* sim-cmd.c -- Simulator command parsing
|
|
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
|
Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
|
Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
|
Copyright (C) 2008 Embecosm Limited
|
Copyright (C) 2008 Embecosm Limited
|
|
Copyright (C) 2011 Giuseppe Scrivano <gscrivano@gnu.org>
|
|
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
|
contributor Giuseppe Scrivano <gscrivano@gnu.org>
|
|
|
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
|
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
|
|
|
This program is free software; you can redistribute it and/or modify it
|
This program is free software; you can redistribute it and/or modify it
|
under the terms of the GNU General Public License as published by the Free
|
under the terms of the GNU General Public License as published by the Free
|
| Line 689... |
Line 691... |
|
|
for (;;)
|
for (;;)
|
{
|
{
|
#ifdef HAVE_LIBREADLINE
|
#ifdef HAVE_LIBREADLINE
|
cur_arg = readline ("(sim) ");
|
cur_arg = readline ("(sim) ");
|
|
|
|
if (!cur_arg)
|
|
{
|
|
sim_done ();
|
|
}
|
#else
|
#else
|
PRINTF ("(sim) ");
|
PRINTF ("(sim) ");
|
|
|
cur_arg = fgets (b2, sizeof (b2), stdin);
|
cur_arg = fgets (b2, sizeof (b2), stdin);
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.