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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.c] - Diff between revs 93 and 100

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Rev 93 Rev 100
Line 140... Line 140...
  cpu_state.sprs[SPR_CPUCFGR] = SPR_CPUCFGR_OB32S;
  cpu_state.sprs[SPR_CPUCFGR] = SPR_CPUCFGR_OB32S;
  config.cpu.superscalar      = 0;
  config.cpu.superscalar      = 0;
  config.cpu.hazards          = 0;
  config.cpu.hazards          = 0;
  config.cpu.dependstats      = 0;
  config.cpu.dependstats      = 0;
  config.cpu.sbuf_len         = 0;
  config.cpu.sbuf_len         = 0;
 
  config.cpu.hardfloat        = 0;
 
 
  /* Data cache (IC is set dynamically). Also set relevant SPR bits */
  /* Data cache (IC is set dynamically). Also set relevant SPR bits */
  config.dc.enabled         = 0;
  config.dc.enabled         = 0;
  config.dc.nsets           = 1;
  config.dc.nsets           = 1;
  config.dc.nways           = 1;
  config.dc.nways           = 1;

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