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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.c] - Diff between revs 93 and 100
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| Rev 93 |
Rev 100 |
| Line 140... |
Line 140... |
cpu_state.sprs[SPR_CPUCFGR] = SPR_CPUCFGR_OB32S;
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cpu_state.sprs[SPR_CPUCFGR] = SPR_CPUCFGR_OB32S;
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config.cpu.superscalar = 0;
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config.cpu.superscalar = 0;
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config.cpu.hazards = 0;
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config.cpu.hazards = 0;
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config.cpu.dependstats = 0;
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config.cpu.dependstats = 0;
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config.cpu.sbuf_len = 0;
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config.cpu.sbuf_len = 0;
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config.cpu.hardfloat = 0;
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/* Data cache (IC is set dynamically). Also set relevant SPR bits */
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/* Data cache (IC is set dynamically). Also set relevant SPR bits */
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config.dc.enabled = 0;
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config.dc.enabled = 0;
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config.dc.nsets = 1;
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config.dc.nsets = 1;
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config.dc.nways = 1;
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config.dc.nways = 1;
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