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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
[/] [openrisc/] [trunk/] [or1ksim/] [sim-config.h] - Diff between revs 19 and 82
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Rev 19 |
Rev 82 |
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Line 151... |
int gdb_enabled; /* Is legacy debugging with GDB possible */
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int gdb_enabled; /* Is legacy debugging with GDB possible */
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int rsp_enabled; /* Is RSP debugging with GDB possible */
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int rsp_enabled; /* Is RSP debugging with GDB possible */
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int server_port; /* Port for legacy GDB connection */
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int server_port; /* Port for legacy GDB connection */
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int rsp_port; /* Port for RSP GDB connection */
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int rsp_port; /* Port for RSP GDB connection */
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unsigned long vapi_id; /* "Fake" vapi dev id for JTAG proxy */
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unsigned long vapi_id; /* "Fake" vapi dev id for JTAG proxy */
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long int jtagcycle_ps; /* JTAG clock duration in ps */
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} debug;
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} debug;
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};
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};
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/*! Data structure for run time data */
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/*! Data structure for run time data */
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struct runtime
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struct runtime
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int hush; /* Is simulator to do reg dumps */
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int hush; /* Is simulator to do reg dumps */
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} sim;
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} sim;
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struct
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struct
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{
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{
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unsigned int instr; /* Current JTAG instruction */
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unsigned long int mod_id; /* Currently selected module */
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int write_defined_p; /* WRITE_COMMAND has set details for GO */
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unsigned char acc_type; /* Access type for GO */
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unsigned long int addr; /* Address to read/write for GO */
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unsigned long int size; /* Number of bytes to read/write */
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} debug;
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struct
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{
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long long instructions; /* Instructions executed */
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long long instructions; /* Instructions executed */
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long long reset_instructions;
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long long reset_instructions;
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int stalled;
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int stalled;
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int hazardwait; /* how many cycles were wasted because of hazards */
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int hazardwait; /* how many cycles were wasted because of hazards */
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