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/* sim.cfg -- Simulator configuration script file
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/* sim.cfg -- Simulator configuration script file
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Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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It contains the default configuration and help about configuring
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the simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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along with this program; if not, write to the Free Software
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Copyright (C) 2010, Embecosm Limited
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* INTRODUCTION
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The ork1sim has various parameters, that are set in configuration files
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like this one. The user can switch between configurations at startup by
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specifying the required configuration file with the -f option.
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If no configuration file is specified or1ksim searches for the default
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configuration file sim.cfg. First it searches for './sim.cfg'. If this
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file is not found, it searches for '~/or1k/sim.cfg'. If this file is
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not found too, it reverts to the built-in default configuration.
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NOTE: Users should not rely on the built-in configuration, since the
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Contributor Jeremy Bennett
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default configuration may differ between version.
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Rather create a configuration file that sets all critical values.
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This file may contain (standard C) comments only - no // support.
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This file is part of OpenRISC 1000 Architectural Simulator.
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Configure files may be be included, using:
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This program is free software; you can redistribute it and/or modify it
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include "file_name_to_include"
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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/* -------------------------------------------------------------------------- */
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/* The Ork1sim has various parameters, that can be set in configuration files
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like this one. The user can specify a configuration file at startu[ with
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the -f option.
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The user guide (see the 'doc' directory) gives full details on
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configuration files. This is a reference configuration, which may be used
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as a starting point for customization.
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A number of peripherals are mapped at standard addresses (above 0x80000000)
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in the Verilog RTL of ORPSoC standard sitribution. The same values should
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be used in Or1ksim section definitions to match the behavior of the Verilog
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0x90000000 UART
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0x91000000 GPIO
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0x92000000 Ethernet
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0x93000000 Memory controller
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0x94000000 PS2 keyboard
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0x97000000 Frame buffer
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0x97100000 VGA
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0x9a000000 DMA controller
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0x9e000000 ATA disc
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Section ordering matches that in the user guide. All optional peripherals
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and functionality is disabled. Comments only list the possible entries and
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values. Consult the user guide for their meaning.
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Like normal configuration files, the included file is divided into
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Unless otherwise indicated, the first named option is the default. */
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sections. Each section is described in detail also.
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/* -------------------------------------------------------------------------- */
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Some section have subsections. One example of such a subsection is:
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device
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/* Simulator section
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instance specific parameters...
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enddevice
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which creates a device instance.
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verbose = 0|1
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debug = 0-9
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profile = 0|1
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prof_file = "" (default: "sim.profile")
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mprofile = 0|1
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mprof_file = "" (default: "sim.mprofile")
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history = 0|1
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exe_log = 0|1
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exe_log_type = hardware|simple|software|default
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exe_log_start = (default: 0)
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exe_log_end = (default: never end)
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exe_log_marker = (default: no markers)
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exe_log_file = "" (default: "executed.log")
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exe_bin_insn_log = 0|1
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exe_bin_insn_log_file = "" (default: "exe-insn.bin")
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clkcycle = [ps|ns|us|ms]
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*/
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*/
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section sim
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clkcycle = 100ns
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end
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/* MEMORY SECTION
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/* VAPI section
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This section specifies how the memory is generated and the blocks
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it consists of.
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type = random/unknown/pattern
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Specifies the initial memory values.
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'random' generates random memory using seed 'random_seed'.
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'pattern' fills memory with 'pattern'.
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'unknown' does not specify how memory should be generated,
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leaving the memory in a undefined state. This is the fastest
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option.
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random_seed =
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enabled = 0|1
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random seed for randomizer, used if type = 'random'.
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server_port = (default: 50000)
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log_enabled = 0|1
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hide_device_id = 0|1
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vapi_log_file = "" (default "vapi.log")
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*/
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section VAPI
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server_port = 50000
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log_enabled = 0
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vapi_log_file = "vapi.log"
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end
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pattern =
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pattern to fill memory, used if type = 'pattern'.
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baseaddr =
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/* CUC section
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memory start address
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size =
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memory_order = none|weak|strong|exact (default: strong)
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memory size
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calling_convention = 0|1
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enable_bursts = 0|1
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no_multicycle = 0|1
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timings_file = "" (default: virtex.tim)
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*/
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section cuc
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memory_order = weak
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calling_convention = 1
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enable_bursts = 1
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no_multicycle = 1
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end
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name = ""
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memory block name
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ce =
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/* CPU section
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chip enable index of the memory instance
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mc =
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ver = (default: 0)
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memory controller this memory is connected to
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cfg = (default: 0)
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rev = (default: 0)
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upr = (see user manual for default settings)
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cfgr = (default: 0x00000020)
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sr = (default: 0x00008001)
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superscalar = 0|1
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hazards = 0|1
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dependstats = 0|1
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sbuf_len = (default: 0)
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hardfloat = 0|1
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*/
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section cpu
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ver = 0x12
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cfg = 0x00
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rev = 0x0001
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end
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delayr =
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cycles, required for read access, -1 if instance does not support reading
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delayw =
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/* Memory section
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cycles, required for write access, -1 if instance does not support
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writing
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log = ""
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type = unknown|random|unknown|pattern
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filename, where to log memory accesses to. If log command is not
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random_seed = (default: -1)
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specified, accesses are not logged.
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pattern = (default: 0)
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baseaddr = (default: 0)
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size = (default: 1024)
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name = "" (default: "anonymous memory block")
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ce = (default: -1)
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mc = (default: 0)
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delayr = (default: 1)
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delayw = (default: 1)
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log = "" (default: NULL)
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*/
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*/
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section memory
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section memory
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name = "RAM"
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name = "RAM"
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random_seed = 12345
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type = unknown
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type = random
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ce = 0
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mc = 0
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baseaddr = 0x00000000
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baseaddr = 0x00000000
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size = 0x00400000
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size = 0x00800000
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delayr = 1
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delayr = 1
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delayw = 2
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delayw = 2
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end
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end
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/* IMMU SECTION
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This section configures the Instruction Memory Manangement Unit
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enabled = 0/1
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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nsets =
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number of ITLB sets; must be power of two
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nways =
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number of ITLB ways
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pagesize =
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instruction page size; must be power of two
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entrysize =
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instruction entry size in bytes
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ustates =
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/* Data MMU section
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number of ITLB usage states (2, 3, 4 etc., max is 4)
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hitdelay =
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enabled = 0|1
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number of cycles immu hit costs
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nsets = (default: 1)
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nways = (default: 1)
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missdelay =
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pagesize = (default: 8192)
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number of cycles immu miss costs
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entrysize = (default: 1)
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ustates = (default: 1)
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hitdelay = (default: 1)
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missdelay = (default: 1)
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*/
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*/
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section dmmu
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section immu
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enabled = 0
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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pagesize = 8192
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pagesize = 8192
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hitdelay = 0
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hitdelay = 0
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missdelay = 0
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missdelay = 0
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end
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end
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/* DMMU SECTION
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/* Instruction MMU section
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This section configures the Data Memory Manangement Unit
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enabled = 0/1
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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nsets =
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number of DTLB sets; must be power of two
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nways =
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enabled = 0|1
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number of DTLB ways
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nsets = (default: 1)
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nways = (default: 1)
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pagesize =
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pagesize = (default: 8192)
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data page size; must be power of two
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entrysize = (default: 1)
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ustates = (default: 1)
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entrysize =
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hitdelay = (default: 1)
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data entry size in bytes
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missdelay = (default: 1)
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ustates =
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number of DTLB usage states (2, 3, 4 etc., max is 4)
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hitdelay =
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number of cycles dmmu hit costs
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missdelay =
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number of cycles dmmu miss costs
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*/
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*/
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section immu
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section dmmu
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enabled = 0
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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pagesize = 8192
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pagesize = 8192
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hitdelay = 0
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hitdelay = 0
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missdelay = 0
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missdelay = 0
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end
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end
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/* IC SECTION
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/* Data cache section
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This section configures the Instruction Cache
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enabled = 0/1
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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nsets =
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number of IC sets; must be power of two
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nways =
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number of IC ways
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blocksize =
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IC block size in bytes; must be power of two
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ustates =
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number of IC usage states (2, 3, 4 etc., max is 4)
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hitdelay =
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number of cycles ic hit costs
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missdelay =
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enabled = 0|1
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number of cycles ic miss costs
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nsets = (default: 1)
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*/
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nways = (default: 1)
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blocksize = (default: 16)
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section ic
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ustates = (default: 2)
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enabled = 1
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load_hitdelay = (default: 2)
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nsets = 256
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load_missdelay = (default: 2)
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nways = 1
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store_hitdelay = (default: 0)
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blocksize = 16
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store_missdelay = (default: 0)
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hitdelay = 0
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missdelay = 0
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end
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/* DC SECTION
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This section configures the Data Cache
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enabled = 0/1
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'0': disabled
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'1': enabled
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(NOTE: UPR bit is set)
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nsets =
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number of DC sets; must be power of two
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nways =
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number of DC ways
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blocksize =
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DC block size in bytes; must be power of two
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ustates =
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number of DC usage states (2, 3, 4 etc., max is 4)
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load_hitdelay =
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number of cycles dc load hit costs
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load_missdelay =
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number of cycles dc load miss costs
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store_hitdelay =
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number of cycles dc store hit costs
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store_missdelay =
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number of cycles dc store miss costs
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*/
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*/
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section dc
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section dc
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enabled = 1
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enabled = 0
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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blocksize = 16
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blocksize = 16
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load_hitdelay = 0
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load_hitdelay = 0
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load_missdelay = 0
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load_missdelay = 0
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store_hitdelay = 0
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store_hitdelay = 0
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store_missdelay = 0
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store_missdelay = 0
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end
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end
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/* PIC SECTION
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/* Instruction cache section
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This section specifies how the pic should behave
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enabled = 0/1
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'0': PIC is disabled
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'1': PIC is enabled
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edge_trigger = 0/1
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'0': Level triggered PIC
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'1': Edge triggered PIC
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*/
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section pic
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enabled = 1
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edge_trigger = 1
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end
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/* SIM SECTION
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This section specifies how or1ksim should behave.
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verbose = 0/1
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'0': don't print extra messages
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'1': print extra messages
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debug = 0-9
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0 : no debug messages
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1-9: debug message level.
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higher numbers produce more messages
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profile = 0/1
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'0': don't generate profiling file 'sim.profile'
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'1': don't generate profiling file 'sim.profile'
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prof_file = ""
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optional filename for the profiling file.
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valid only if 'profile' is set
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mprofile = 0/1
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'0': don't generate memory profiling file 'sim.mprofile'
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'1': generate memory profiling file 'sim.mprofile'
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mprof_file = ""
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optional filename for the memory profiling file.
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valid only if 'mprofile' is set
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history = 0/1
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'0': don't track execution flow
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'1': track execution flow
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Execution flow can be tracked for the simulator's
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'hist' command. Useful for back-trace debugging.
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iprompt = 0/1
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'0': start in (so what do we start in ???)
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'1': start in interactive prompt.
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exe_log = 0/1
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'0': don't generate execution log.
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'1': generate execution log.
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exe_log_type = default/hardware/simple/software
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type of execution log, default is used when not specified
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exe_log_start =
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index of first instruction to start logging, default = 0
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exe_log_end =
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index of last instruction to end logging; not limited, if omitted
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exe_log_marker =
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specifies number of instructions before horizontal marker is
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printed; if zero, markers are disabled (default)
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exe_log_file = ""
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filename for the exection log file.
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valid only if 'exe_log' is set
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clkcycle = [ps|ns|us|ms]
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specifies time measurement for one cycle
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*/
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section sim
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/* verbose = 1 */
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debug = 0
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profile = 0
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prof_file = "sim.profile"
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history = 0
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/* iprompt = 0 */
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exe_log = 0
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exe_log_type = software
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exe_log_start = 0
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/* exe_log_end = 20000000*/
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exe_log_marker = 10000
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exe_log_file = "executed.log"
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clkcycle = 100ns
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end
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/* SECTION VAPI
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This section configures the Verification API, used for Advanced
|
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Core Verification.
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enabled = 0/1
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'0': disbable VAPI server
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'1': enable/start VAPI server
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server_port =
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TCP/IP port to start VAPI server on
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log_enabled = 0/1
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'0': disable VAPI requests logging
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'1': enable VAPI requests logging
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hide_device_id = 0/1
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'1': don't log device id (for compatability with old version)
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'0': log device id
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enabled = 0|1
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vapi_log_file =
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nsets = (default: 1)
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filename for the log file.
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nways = (default: 1)
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valid only if log_enabled is set
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blocksize = (default: 16)
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ustates = (default: 2)
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hitdelay = (default: 1)
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missdelay = (default: 1)
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*/
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*/
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section ic
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section VAPI
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enabled = 0
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enabled = 0
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server_port = 50000
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nsets = 256
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log_enabled = 0
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nways = 1
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vapi_log_file = "vapi.log"
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blocksize = 16
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hitdelay = 0
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missdelay = 0
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end
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end
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/* CPU SECTION
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/* Programmable interrupt controller section
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|
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This section specifies various CPU parameters.
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ver =
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enabled = 0|1
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cfg =
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edge_trigger = 0|1 (default: 1)
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rev =
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specifies version, configuration and revision fields of the CPU version
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register.
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upr =
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changes the upr register
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cfgr =
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changes the CPU configuration register
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sr =
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sets the initial Supervision Register value
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superscalar = 0/1
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'0': CPU is scalar
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'1': CPU is superscalar
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(modify cpu/or32/execute.c to tune superscalar model)
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hazards = 0/1
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'0': don't track data hazards in superscalar CPU
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'1': track data hazards in superscalar CPU
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If tracked, data hazards can be displayed using the
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simulator's 'r' command.
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|
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dependstats = 0/1
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'0': don't calculate inter-instruction dependencies.
|
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'1': calculate inter-instruction dependencies.
|
|
If calculated, inter-instruction dependencies can be
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displayed using the simulator's 'stat' command.
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|
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sbuf_len =
|
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length of store buffer (<= 256), 0 = disabled
|
|
*/
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*/
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|
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section cpu
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section pic
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ver = 0x12
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enabled = 0
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cfg = 0x00
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rev = 0x0001
|
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superscalar = 0
|
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hazards = 0
|
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dependstats = 0
|
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sbuf_len = 0
|
|
end
|
end
|
|
|
|
|
/* PM SECTION
|
/* Power management section
|
|
|
This section specifies Power Management parameters
|
enabled = 0|1
|
|
|
enabled = 0/1
|
|
'0': disable power management
|
|
'1': enable power management
|
|
*/
|
*/
|
|
|
section pm
|
section pm
|
enabled = 1
|
enabled = 0
|
end
|
end
|
|
|
|
|
/* BPB SECTION
|
/* Branch prediction section
|
|
|
This section specifies how branch prediction should behave.
|
|
|
|
enabled = 0/1
|
|
'0': disable branch prediction
|
|
'1': enable branch prediction
|
|
|
|
btic = 0/1
|
|
'0': disable branch target instruction cache model
|
|
'1': enable branch target instruction cache model
|
|
|
|
sbp_bf_fwd = 0/1
|
enabled = 0|1
|
Static branch prediction for 'l.bf'
|
btic = 0|1
|
'0': don't use forward prediction
|
sbp_bf_fwd = 0|1
|
'1': use forward prediction
|
sbp_bnf_fwd = 0|1
|
|
hitdelay = (default: 0)
|
sbp_bnf_fwd = 0/1
|
missdelay = (default: 0)
|
Static branch prediction for 'l.bnf'
|
|
'0': don't use forward prediction
|
|
'1': use forward prediction
|
|
|
|
hitdelay =
|
|
number of cycles bpb hit costs
|
|
|
|
missdelay =
|
|
number of cycles bpb miss costs
|
|
*/
|
*/
|
|
|
section bpb
|
section bpb
|
enabled = 1
|
enabled = 0
|
btic = 0
|
|
sbp_bf_fwd = 0
|
|
sbp_bnf_fwd = 0
|
|
hitdelay = 0
|
|
missdelay = 0
|
|
end
|
end
|
|
|
|
|
/* DEBUG SECTION
|
/* Debug unit section
|
|
|
This sections specifies how the debug unit should behave.
|
|
|
|
enabled = 0/1
|
|
'0': disable debug unit
|
|
'1': enable debug unit
|
|
|
|
gdb_enabled = 0/1
|
enabled = 0|1
|
'0': don't start gdb server
|
rsp_enabled = 0|1
|
'1': start gdb server at port 'server_port'
|
rsp_port = (default: 51000)
|
|
vapi_id = (default: 0)
|
server_port =
|
|
TCP/IP port to start gdb server on
|
|
valid only if gdb_enabled is set
|
|
|
|
vapi_id =
|
|
Used to create "fake" vapi log file containing the JTAG proxy messages.
|
|
*/
|
*/
|
|
|
section debug
|
section debug
|
enabled = 0
|
enabled = 0
|
gdb_enabled = 0
|
|
server_port = 51000
|
|
end
|
end
|
|
|
|
|
/* MC SECTION
|
/* Memory controller section
|
|
|
This section configures the memory controller
|
|
|
|
enabled = 0/1
|
|
'0': disable memory controller
|
|
'1': enable memory controller
|
|
|
|
baseaddr =
|
enabled = 0|1
|
address of first MC register
|
baseaddr = (default: 0)
|
|
POC = (default: 0)
|
POC =
|
index = (default: 0)
|
Power On Configuration register
|
|
|
|
index =
|
|
Index of this memory controller amongst all the memory controllers
|
|
*/
|
*/
|
|
|
section mc
|
section mc
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x93000000
|
baseaddr = 0x93000000
|
POC = 0x0000000a /* 32 bit SSRAM */
|
POC = 0x0000000a /* 32 bit SSRAM */
|
index = 0
|
index = 0
|
end
|
end
|
|
|
|
|
/* UART SECTION
|
/* UART section
|
|
|
This section configures the UARTs
|
|
|
|
enabled = <0|1>
|
|
Enable/disable the peripheral. By default if it is enabled.
|
|
|
|
baseaddr =
|
|
address of first UART register for this device
|
|
|
|
|
|
channel = :
|
|
|
|
The channel parameter indicates the source of received UART characters
|
|
and the sink for transmitted UART characters.
|
|
|
|
The can be either "file", "xterm", "tcp", "fd", or "tty"
|
|
(without quotes).
|
|
|
|
A) To send/receive characters from a pair of files, use a file
|
|
channel:
|
|
|
|
channel=file:,
|
enabled = 0|1
|
|
baseaddr = (default: 0)
|
B) To create an interactive terminal window, use an xterm channel:
|
channel = "value>" (default: "xterm:")
|
|
irq = (default: 0)
|
channel=xterm:[]*
|
16550 = 0|1
|
|
jitter = (default: 0)
|
C) To create a bidirectional tcp socket which one could, for example,
|
vapi_id = (default: 0)
|
access via telnet, use a tcp channel:
|
|
|
|
channel=tcp:
|
|
|
|
D) To cause the UART to read/write from existing numeric file
|
|
descriptors, use an fd channel:
|
|
|
|
channel=fd:,
|
|
|
|
E) To connect the UART to a physical serial port, create a tty
|
|
channel:
|
|
|
|
channel=tty:device=/dev/ttyS0,baud=9600
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
16550 = 0/1
|
|
'0': this device is a UART16450
|
|
'1': this device is a UART16550
|
|
|
|
jitter =
|
|
in msecs... time to block, -1 to disable it
|
|
|
|
vapi_id =
|
|
VAPI id of this instance
|
|
*/
|
*/
|
|
|
section uart
|
section uart
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x90000000
|
baseaddr = 0x90000000
|
irq = 2
|
irq = 2
|
channel = "file:uart0.rx,uart0.tx"
|
|
jitter = -1 /* async behaviour */
|
|
16550 = 1
|
16550 = 1
|
end
|
end
|
|
|
|
|
/* DMA SECTION
|
/* DMA section
|
|
|
This section configures the DMAs
|
|
|
|
enabled = <0|1>
|
|
Enable/disable the peripheral. By default if it is enabled.
|
|
|
|
baseaddr =
|
|
address of first DMA register for this device
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
vapi_id =
|
enabled = 0|1
|
VAPI id of this instance
|
baseaddr = (default: 0)
|
|
irq = (default: 0)
|
|
vapi_id = (default: 0)
|
*/
|
*/
|
|
|
section dma
|
section dma
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x9a000000
|
baseaddr = 0x9a000000
|
irq = 11
|
irq = 11
|
end
|
end
|
|
|
|
|
/* ETHERNET SECTION
|
/* Ethernet section
|
|
|
This section configures the ETHERNETs
|
|
|
|
enabled = <0|1>
|
|
Enable/disable the peripheral. By default if it is enabled.
|
|
|
|
baseaddr =
|
|
address of first ethernet register for this device
|
|
|
|
dma =
|
|
which controller is this ethernet "connected" to
|
|
|
|
irq =
|
|
ethernet mac IRQ level
|
|
|
|
rtx_type =
|
|
use 0 - file interface, 1 - socket interface. Note the socket
|
|
interface must be configured at build time.
|
|
|
|
rx_channel =
|
enabled = 0|1
|
DMA channel used for RX
|
baseaddr = (default: 0)
|
|
dma = (default: 0)
|
tx_channel =
|
irq = (default: 0)
|
DMA channel used for TX
|
rtx_type = 0|1
|
|
rx_channel = (default: 0)
|
rxfile = ""
|
tx_channel = (default: 0)
|
filename, where to read data from
|
rxfile = "" (default: "eth_rx")
|
|
txfile = "" (default: "eth_rx")
|
txfile = ""
|
sockif = "" (default: "or1ksim_eth")
|
filename, where to write data to
|
vapi_id = (default: 0)
|
|
|
sockif = ""
|
|
interface name of ethernet socket
|
|
|
|
vapi_id =
|
|
VAPI id of this instance
|
|
*/
|
*/
|
|
|
section ethernet
|
section ethernet
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x92000000
|
baseaddr = 0x92000000
|
irq = 4
|
irq = 4
|
rtx_type = 0
|
rtx_type = 0
|
rxfile = "eth0.rx"
|
|
txfile = "eth0.tx"
|
|
sockif = "eth0"
|
|
end
|
end
|
|
|
|
|
/* GPIO SECTION
|
/* GPIO section
|
|
|
This section configures the GPIOs
|
enabled = 0|1
|
|
baseaddr = (default: 0)
|
enabled = <0|1>
|
irq = (default: 0)
|
Enable/disable the peripheral. By default if it is enabled.
|
base_vapi_id = (default: 0)
|
|
|
baseaddr =
|
|
address of first GPIO register for this device
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
base_vapi_id =
|
|
first VAPI id of this instance
|
|
GPIO uses 8 consecutive VAPI IDs
|
|
*/
|
*/
|
|
|
section gpio
|
section gpio
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x91000000
|
baseaddr = 0x91000000
|
irq = 3
|
irq = 3
|
base_vapi_id = 0x0200
|
base_vapi_id = 0x0200
|
end
|
end
|
|
|
/* VGA SECTION
|
/* VGA section
|
|
|
This section configures the VGA/LCD controller
|
|
|
|
enabled = <0|1>
|
|
Enable/disable the peripheral. By default if it is enabled.
|
|
|
|
baseaddr =
|
enabled = 0|1
|
address of first VGA register
|
baseaddr = (default: 0)
|
|
irq = (default: 0)
|
irq =
|
refresh_rate = (default: cycles equivalent to 50Hz)
|
irq number for this device
|
filename = "" (default: "vga_out))
|
|
|
refresh_rate =
|
|
number of cycles between screen dumps
|
|
|
|
filename = ""
|
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
|
*/
|
*/
|
|
|
section vga
|
section vga
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x97100000
|
baseaddr = 0x97100000
|
irq = 8
|
irq = 8
|
refresh_rate = 100000
|
|
filename = "primary"
|
|
end
|
end
|
|
|
|
|
/* FB SECTION
|
/* Frame buffer section
|
|
|
This section configures the frame buffer
|
|
|
|
enabled = <0|1>
|
|
Enable/disable the peripheral. By default if it is enabled.
|
|
|
|
baseaddr =
|
|
base address of frame buffer
|
|
|
|
refresh_rate =
|
enabled = 0|1
|
number of cycles between screen dumps
|
baseaddr = (default: 0)
|
|
refresh_rate = (default: cycles equivalent to 50Hz)
|
filename = ""
|
filename = "" (default: "fb_out))
|
template name for generated names (e.g. "primary" produces "primary0023.bmp")
|
|
*/
|
*/
|
|
|
section fb
|
section fb
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x97000000
|
baseaddr = 0x97000000
|
refresh_rate = 1000000
|
|
filename = "primary"
|
|
end
|
end
|
|
|
|
|
/* KBD SECTION
|
/* PS2 keyboard section
|
|
|
This section configures the PS/2 compatible keyboard
|
This section configures the PS/2 compatible keyboard
|
|
|
enabled = <0|1>
|
enabled = 0|1
|
Enable/disable the peripheral. By default if it is enabled.
|
baseaddr = (default: 0)
|
|
irq = (default: 0)
|
baseaddr =
|
rxfile = "" (default: "kbd_in")
|
base address of the keyboard device
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
rxfile = ""
|
|
filename, where to read data from
|
|
*/
|
*/
|
|
|
section kbd
|
section kbd
|
enabled = 1
|
enabled = 1
|
baseaddr = 0x94000000
|
baseaddr = 0x94000000
|
irq = 5
|
irq = 5
|
rxfile = "kbd.rx"
|
|
end
|
end
|
|
|
|
|
/* ATA SECTION
|
/* ATA disc section
|
|
|
This section configures the ATA/ATAPI host controller
|
|
|
|
enabled = <0|1>
|
|
Enable/disable the peripheral. By default it is enabled.
|
|
|
|
baseaddr =
|
|
address of first ATA register
|
|
|
|
irq =
|
|
irq number for this device
|
|
|
|
dev_id = 1/2/3
|
|
Which OCIDEC version to imitate
|
|
|
|
rev =
|
|
Revision of OCIDEC
|
|
|
|
pio_mode0_t1 = <0-255>
|
|
PIO T1 reset value
|
|
|
|
pio_mode0_t2 = <0-255>
|
|
PIO T2 reset value
|
|
|
|
pio_mode0_t4 = <0-255>
|
|
PIO T4 reset value
|
|
|
|
pio_mode0_teoc = <0-255>
|
enabled = 0|1
|
PIO Teoc reset value
|
baseaddr = (default: 0)
|
|
irq = (default: 0)
|
dma_mode0_tm = <0-255>
|
dev_id = 1|2|3
|
DMA Tm reset value
|
rev = 0-15 (default: 1)
|
|
pio_mode0_t1 = 0-255 (default: 6)
|
dma_mode0_td = <0-255>
|
pio_mode0_t2 = 0-255 (default: 28)
|
DMA Td reset value
|
pio_mode0_t4 = 0-255 (default: 2)
|
|
pio_mode0_teoc = 0-255 (default: 23)
|
dma_mode0_teoc = <0-255>
|
dma_mode0_tm = 0-255 (default: 4)
|
DMA Teoc reset value
|
dma_mode0_td = 0-255 (default: 21)
|
|
dma_mode0_teoc = 0-255 (default: 21)
|
Device specific
|
device = 0|1
|
|
|
type =
|
Device specific:
|
ata device 0 type
|
|
0: NO_CONNECT: none (not connected)
|
type = 0|1|2
|
1: FILE : simulated harddisk
|
file = "" (default: "ata_file")
|
2: LOCAL : local system harddisk
|
size = (default: 0)
|
|
packet = 0|1
|
file = ""
|
firmware = "" (default: "02207031")
|
filename for simulated ATA device
|
heads = (default: 7)
|
valid only if dev_type0 == 1
|
sectors = (default: 32)
|
|
mwdma = 2|1|0|-1
|
size =
|
pio = 4|3|2|1|0
|
size of simulated hard-disk (in MBytes)
|
|
valid only if dev_type0 == 1
|
|
|
|
packet =
|
|
0: simulated ATA device does NOT implement PACKET command feature set
|
|
1: simulated ATA device does implement PACKET command feature set
|
|
|
|
firmware =
|
|
Firmware to report in `Identify device command'
|
|
|
|
heads =
|
|
Number of default heads (-1)
|
|
|
|
sectors =
|
|
Number of default sectors per track
|
|
|
|
mwdma =
|
|
The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
|
|
|
|
pio =
|
|
The highest supported pio mode; 4, 3, 2, 1, 0
|
|
|
|
FIXME: irq number
|
|
*/
|
*/
|
|
|
section ata
|
section ata
|
enabled = 1
|
enabled = 0
|
baseaddr = 0x9e000000
|
baseaddr = 0x9e000000
|
irq = 15
|
irq = 15
|
dev_id = 1
|
|
rev = 0
|
|
|
|
pio_mode0_t1 = 6
|
|
pio_mode0_t2 = 28
|
|
pio_mode0_t4 = 2
|
|
pio_mode0_teoc = 23
|
|
|
|
dma_mode0_tm = 4
|
|
dma_mode0_td = 21
|
|
dma_mode0_teoc = 21
|
|
|
|
device 0
|
device 0
|
type = 1
|
type = 1
|
file = "/tmp/sim_atadev0"
|
|
size = 1
|
size = 1
|
packet = 0
|
|
|
|
heads = 7
|
|
sectors = 32
|
|
|
|
firmware = "02207031"
|
|
mwdma = 2
|
|
pio = 4
|
|
enddevice
|
|
|
|
device 1
|
|
type = 0
|
|
file = ""
|
|
size = 0
|
|
packet = 0
|
|
enddevice
|
enddevice
|
end
|
end
|
|
|
|
|
/* CUC SECTION
|
/* Generic peripheral section
|
|
|
This section configures the OpenRISC Custom Unit Compiler
|
|
|
|
memory_order = none/weak/strong/exact
|
|
none different memory ordering, even if there are dependencies,
|
|
burst can be made, width can change
|
|
weak different memory ordering, if there cannot be dependencies
|
|
burst can be made, width can change
|
|
strong same memory ordering, burst can be made, width can change
|
|
exact exacltly the same memory ordering and widths
|
|
|
|
calling_convention = 0/1
|
|
whether programs follow OpenRISC calling conventions
|
|
|
|
enable_bursts = 0/1
|
|
whether burst are detected
|
|
|
|
no_multicycle = 0/1
|
|
if selected no multicycle logic paths will be generated
|
|
|
|
timings_fn = ""
|
enabled = 0|1
|
|
baseaddr = (default: 0)
|
|
size = (default: 0)
|
|
name = "" (default: "anonymous external peripheral")
|
|
byte_enabled = 1|0
|
|
hw_enabled = 1|0
|
|
word_enabled = 1|0
|
*/
|
*/
|
|
section generic
|
section cuc
|
enabled = 0
|
memory_order = weak
|
|
calling_convention = 1
|
|
enable_bursts = 1
|
|
no_multicycle = 1
|
|
timings_fn = "virtex.tim"
|
|
end
|
end
|
|
|
