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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 434 |
Rev 458 |
| Line 25... |
Line 25... |
/*random_seed = 12345
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/*random_seed = 12345
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type = random*/
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type = random*/
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pattern = 0x00
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pattern = 0x00
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type = unknown /* Fastest */
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type = unknown /* Fastest */
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name = "FLASH"
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ce = 0
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mc = 0
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baseaddr = 0xf0000000
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size = 0x00200000
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delayr = 10
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delayw = -1
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end
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section memory
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/*random_seed = 12345
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type = random*/
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pattern = 0x00
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type = unknown /* Fastest */
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name = "RAM"
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name = "RAM"
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ce = 1
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ce = 1
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mc = 0
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mc = 0
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baseaddr = 0x00000000
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baseaddr = 0x00000000
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size = 0x00200000
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size = 0x00200000
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| Line 102... |
Line 87... |
/* Set the CPU to take vectors at 0xf0000000 */
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/* Set the CPU to take vectors at 0xf0000000 */
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section cpu
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section cpu
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ver = 0x12
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ver = 0x12
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rev = 0x0001
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rev = 0x0001
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/* upr = */
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/* upr = */
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sr = 0xc001
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sr = 0x8001
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superscalar = 0
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superscalar = 0
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hazards = 0
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hazards = 0
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dependstats = 0
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dependstats = 0
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end
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end
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| Line 128... |
Line 113... |
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exe_log = 0
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exe_log = 0
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exe_log_type = software
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exe_log_type = software
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exe_log_fn = "executed.log"
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exe_log_fn = "executed.log"
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end
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end
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/* Memory instead of MC. Stops write errors when the startup code tries to
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access a non-existent MC */
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section memory
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/*random_seed = 12345
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type = random*/
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pattern = 0x00
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type = unknown /* Fastest */
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name = "MC shadow"
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baseaddr = 0x93000000
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size = 0x00000080
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delayr = 2
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delayw = 4
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end
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/* Disabled */
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section mc
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enabled = 0
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baseaddr = 0x93000000
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POC = 0x00000008 /* Power on configuration register */
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index = 0
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end
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section dma
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baseaddr = 0xB8000000
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irq = 4
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end
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section ethernet
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enabled = 0
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baseaddr = 0x92000000
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irq = 4
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rtx_type = "file"
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end
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section VAPI
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enabled = 0
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server_port = 9998
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end
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section fb
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enabled = 1
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baseaddr = 0x97000000
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refresh_rate = 10000
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filename = "primary"
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end
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section kbd
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enabled = 0
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end
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