OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [or1ksim.tests/] [mmu.cfg] - Diff between revs 82 and 458

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 82 Rev 458
Line 79... Line 79...
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
  blocksize = 16
  blocksize = 16
end
end
 
 
 
section cpu
 
  ver =   0x12
 
  rev = 0x0001
 
  /* upr = */
 
  superscalar = 0
 
  hazards = 0
 
  dependstats = 0
 
end
 
 
section sim
section sim
  /* verbose = 1 */
  /* verbose = 1 */
  debug = 0
  debug = 0
  profile = 0
  profile = 0
  prof_fn = "sim.profile"
  prof_fn = "sim.profile"
Line 90... Line 99...
  history = 1
  history = 1
  /* iprompt = 0 */
  /* iprompt = 0 */
  exe_log = 0
  exe_log = 0
  exe_log_fn = "executed.log"
  exe_log_fn = "executed.log"
end
end
 
 
section mc
 
  enabled = 1
 
  baseaddr = 0x93000000
 
  POC = 0x00000008                 /* Power on configuration register */
 
end
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.