URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [ChangeLog] - Diff between revs 784 and 787

Rev 784	Rev 787
Line 1...	Line 1...
	`2012-03-23 Jeremy Bennett`

	`Patch from R Diez`

	`* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,`
	`* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,`
	`* inst-set-test/inst-set-test.S, int-test/int-test.S,`
	`* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on`
	`start-up. There is no guarantee that R0 is hardwired to zero, and`
	`indeed it is not when simulating the or1200 Verilog core.`
	`* configure: Regenerated.`
	`* configure.ac: Updated version.`

`2012-03-21 Jeremy Bennett`	`2012-03-21 Jeremy Bennett`

`* configure: Regenerated.`	`* configure: Regenerated.`
`* configure.ac: Updated version. Added AM_SILENT_RULES for nicer`	`* configure.ac: Updated version.`
`builds.`

`2011-08-15 Jeremy Bennett`	`2011-08-15 Jeremy Bennett`

`* configure: Regenerated.`	`* configure: Regenerated.`
`* configure.ac: Updated version. Added AM_SILENT_RULES for nicer`	`* configure.ac: Updated version. Added AM_SILENT_RULES for nicer`