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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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| Rev 90 |
Rev 458 |
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Line 28... |
#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#define MEM_RAM 0x00000000
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#define MEM_RAM 0x00000000
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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.section .except, "ax"
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l.addi r1,r0,0
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.section .text
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.section .text
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.global main
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.org 0x100
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main:
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_reset:
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l.movhi r1,hi(_init_mc)
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l.ori r1,r1,lo(_init_mc)
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l.jr r1
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l.nop
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l.nop
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_init_mc:
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.srai r5,r5,6
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.srai r5,r5,6
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
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_regs:
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_regs:
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l.addi r1,r0,0x1
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l.addi r1,r0,0x1
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l.addi r2,r1,0x2
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l.addi r2,r1,0x2
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l.addi r3,r2,0x4
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l.addi r3,r2,0x4
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l.addi r4,r3,0x8
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l.addi r4,r3,0x8
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