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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [cache/] [cache-asm.S] - Diff between revs 90 and 346

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Rev 90 Rev 346
Line 36... Line 36...
#define MC_BA_MASK      (0x08)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
 
 
 
        .extern _main
        .extern main
 
 
        .global _ic_enable
        .global ic_enable
        .global _ic_disable
        .global ic_disable
        .global _dc_enable
        .global dc_enable
        .global _dc_disable
        .global dc_disable
        .global _dc_inv
        .global dc_inv
        .global _ic_inv_test
        .global ic_inv_test
        .global _dc_inv_test
        .global dc_inv_test
 
 
        .section .stack
        .section .stack
        .space 0x1000
        .space 0x1000
_stack:
stack:
 
 
        .section .reset, "ax"
        .section .reset, "ax"
 
 
        .org    0x100
        .org    0x100
_reset_vector:
reset_vector:
        l.addi  r2,r0,0x0
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r6,r0,0x0
Line 90... Line 90...
        l.movhi r3,hi(start)
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.jr    r3
        l.nop
        l.nop
start:
start:
        l.jal   _init_mc
        l.jal   init_mc
        l.nop
        l.nop
 
 
        l.movhi r1,hi(_stack)
        l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(_stack)
        l.ori   r1,r1,lo(stack)
 
 
        /* Copy data section */
        /* Copy data section */
        l.movhi r3,hi(_src_beg)
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_dst_beg)
        l.movhi r4,hi(_dst_beg)
Line 116... Line 116...
        l.addi  r5,r5,-4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.sfgtsi r5,0
        l.bf    1b
        l.bf    1b
        l.nop
        l.nop
2:
2:
        l.movhi r2,hi(_main)
        l.movhi r2,hi(main)
        l.ori   r2,r2,lo(_main)
        l.ori   r2,r2,lo(main)
        l.jr    r2
        l.jr    r2
        l.nop
        l.nop
 
 
_init_mc:
init_mc:
 
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
 
        l.addi  r4,r3,MC_CSC(0)
        l.addi  r4,r3,MC_CSC(0)
Line 163... Line 163...
        l.nop
        l.nop
 
 
 
 
        .section .text
        .section .text
 
 
_ic_enable:
ic_enable:
        /* Disable IC */
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.and   r11,r13,r11
Line 193... Line 193...
        l.nop
        l.nop
 
 
        l.jr    r9
        l.jr    r9
        l.nop
        l.nop
 
 
_ic_disable:
ic_disable:
        /* Disable IC */
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
        l.mtspr r0,r11,SPR_SR
 
 
        l.jr    r9
        l.jr    r9
        l.nop
        l.nop
 
 
_dc_enable:
dc_enable:
        /* Disable DC */
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.and   r11,r13,r11
Line 229... Line 229...
        l.mtspr r0,r13,SPR_SR
        l.mtspr r0,r13,SPR_SR
 
 
        l.jr    r9
        l.jr    r9
        l.nop
        l.nop
 
 
_dc_disable:
dc_disable:
        /* Disable DC */
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
        l.mtspr r0,r11,SPR_SR
 
 
        l.jr    r9
        l.jr    r9
        l.nop
        l.nop
 
 
_dc_inv:
dc_inv:
        l.mfspr r4,r0,SPR_SR
        l.mfspr r4,r0,SPR_SR
        l.addi  r5,r0,-1
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r4,r5
        l.and   r5,r4,r5
        l.mtspr r0,r5,SPR_SR
        l.mtspr r0,r5,SPR_SR
Line 252... Line 252...
        l.mtspr r0,r4,SPR_SR
        l.mtspr r0,r4,SPR_SR
        l.jr    r9
        l.jr    r9
        l.nop
        l.nop
 
 
        .align  0x10
        .align  0x10
_ic_inv_test:
ic_inv_test:
        l.movhi r7,hi(_ic_test_1)
        l.movhi r7,hi(ic_test_1)
        l.ori   r7,r7,lo(_ic_test_1)
        l.ori   r7,r7,lo(ic_test_1)
        l.addi  r3,r0,0
        l.addi  r3,r0,0
        l.addi  r4,r0,0
        l.addi  r4,r0,0
        l.addi  r5,r0,0
        l.addi  r5,r0,0
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
 
_ic_test_1:
ic_test_1:
3:      l.addi  r3,r3,1
3:      l.addi  r3,r3,1
 
 
        l.sfeqi r4,0x01
        l.sfeqi r4,0x01
        l.bnf   1f
        l.bnf   1f
        l.nop
        l.nop
Line 292... Line 292...
 
 
        l.addi  r11,r3,0
        l.addi  r11,r3,0
        l.jr    r9
        l.jr    r9
        l.nop
        l.nop
 
 
_dc_inv_test:
dc_inv_test:
        l.movhi r4,hi(0x08040201)
        l.movhi r4,hi(0x08040201)
        l.ori   r4,r4,lo(0x08040201)
        l.ori   r4,r4,lo(0x08040201)
        l.sw    0x00(r3),r4
        l.sw    0x00(r3),r4
        l.slli  r4,r4,1
        l.slli  r4,r4,1
        l.sw    0x14(r3),r4
        l.sw    0x14(r3),r4
        l.slli  r4,r4,1
        l.slli  r4,r4,1
        l.sw    0x28(r3),r4
        l.sw    0x28(r3),r4
 
 
        l.addi  r8,r9,0
        l.addi  r8,r9,0
        l.jal   _dc_enable
        l.jal   dc_enable
        l.nop
        l.nop
        l.addi  r9,r8,0
        l.addi  r9,r8,0
 
 
        l.lbz   r4,0x03(r3)
        l.lbz   r4,0x03(r3)
        l.lhz   r5,0x16(r3)
        l.lhz   r5,0x16(r3)

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