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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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| Rev 346 |
Rev 458 |
| Line 29... |
Line 29... |
#include "board.h"
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#include "board.h"
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#define IC_ENABLE 0
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#define IC_ENABLE 0
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#define DC_ENABLE 0
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#define DC_ENABLE 0
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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.extern main
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.extern main
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.global ic_enable
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.global ic_enable
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.global ic_disable
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.global ic_disable
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.global dc_enable
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.global dc_enable
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| Line 90... |
Line 83... |
l.movhi r3,hi(start)
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l.movhi r3,hi(start)
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l.ori r3,r3,lo(start)
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l.ori r3,r3,lo(start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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start:
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start:
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l.jal init_mc
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l.nop
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l.movhi r1,hi(stack)
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l.movhi r1,hi(stack)
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l.ori r1,r1,lo(stack)
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l.ori r1,r1,lo(stack)
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l.ori r2,r1, 0
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/* Copy data section */
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l.movhi r3,hi(main)
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l.movhi r3,hi(_src_beg)
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l.ori r3,r3,lo(main)
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l.ori r3,r3,lo(_src_beg)
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l.jr r3
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l.movhi r4,hi(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.movhi r5,hi(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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l.sub r5,r5,r4
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l.sfeqi r5,0
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l.bf 2f
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l.nop
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1: l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.bf 1b
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l.nop
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2:
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l.movhi r2,hi(main)
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l.ori r2,r2,lo(main)
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l.jr r2
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l.nop
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init_mc:
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.srai r5,r5,6
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.srai r5,r5,6
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
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l.jr r9
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l.nop
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l.nop
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.section .text
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.section .text
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ic_enable:
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ic_enable:
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/* Disable IC */
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/* Disable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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