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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 458 |
Line 26... |
Line 26... |
--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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MEMORY
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MEMORY
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{
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{
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except : ORIGIN = 0x00000000, LENGTH = 0x00002000
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except : ORIGIN = 0x00000000, LENGTH = 0x00002000
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flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000
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ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
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ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
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}
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}
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SECTIONS
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SECTIONS
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{
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{
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.reset :
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.reset :
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{
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{
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*(.reset)
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*(.reset)
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_src_beg = .;
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_src_beg = .;
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} > flash
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} > except
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.text :
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.text :
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AT ( ADDR (.reset) + SIZEOF (.reset) )
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/* AT ( ADDR (.reset) + SIZEOF (.reset) )*/
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{
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{
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_dst_beg = .;
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_dst_beg = .;
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*(.text)
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*(.text)
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} > ram
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} > ram
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.data :
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.data :
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AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )
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/* AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )*/
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{
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{
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*(.data)
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*(.data)
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*(.data.rel)
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*(.data.rel)
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*(.data.rel.local)
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*(.data.rel.local)
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*(.rodata)
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*(.rodata)
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*(.rodata.*)
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_dst_end = .;
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_dst_end = .;
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} > ram
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} > ram
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.bss :
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.bss :
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{
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{
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*(.bss)
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*(.bss)
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