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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [cfg/] [cfg.S] - Diff between revs 458 and 787

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Rev 458 Rev 787
Line 28... Line 28...
#include "spr-defs.h"
#include "spr-defs.h"
 
 
        .section .except,"ax"
        .section .except,"ax"
        .org 0x100
        .org 0x100
_reset:
_reset:
 
        // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
 
        // and indeed it is not when simulating the or1200 Verilog core.
 
        l.andi  r0,r0,0x0
 
 
        l.addi  r1,r0,0x7f00
        l.addi  r1,r0,0x7f00
        l.movhi r2,hi(_main)
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.jr    r2
        l.nop
        l.nop

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