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| Rev 458 |
Rev 787 |
| Line 56... |
Line 56... |
.section .except,"ax"
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.section .except,"ax"
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.org 0x100
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.org 0x100
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reset_vector:
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reset_vector:
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l.nop
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l.nop
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l.nop
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l.nop
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// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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// and indeed it is not when simulating the or1200 Verilog core.
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l.andi r0,r0,0x0
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l.addi r4,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r6,r0,0x0
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l.addi r7,r0,0x0
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l.addi r7,r0,0x0
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l.addi r8,r0,0x0
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l.addi r8,r0,0x0
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