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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except-test/] [except-test-s.S] - Diff between revs 346 and 458

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Rev 346	Rev 458
Line 28...	Line 28...
`#include "spr-defs.h"`	`#include "spr-defs.h"`
`#include "board.h"`	`#include "board.h"`

`#define reset main`	`#define reset main`

`#define MC_CSR (0x00)`
`#define MC_POC (0x04)`
`#define MC_BA_MASK (0x08)`
`#define MC_CSC(i) (0x10 + (i) * 8)`
`#define MC_TMS(i) (0x14 + (i) * 8)`

`.global except_basic`	`.global except_basic`
`.global lo_dmmu_en`	`.global lo_dmmu_en`
`.global lo_immu_en`	`.global lo_immu_en`
`.global call`	`.global call`
`.global call_with_int`	`.global call_with_int`
Line 72...	Line 66...
`.extern excpt_range`	`.extern excpt_range`
`.extern excpt_syscall`	`.extern excpt_syscall`
`.extern excpt_break`	`.extern excpt_break`
`.extern excpt_trap`	`.extern excpt_trap`

	`/* Our special text section is used to guarantee this code goes first`
	`when linking. */`

`.section .except, "ax"`	`.section .except, "ax"`

	`.org 0x100`
	`reset_vector:`
	`l.nop`
	`l.nop`
	`l.addi r2,r0,0x0`
	`l.addi r3,r0,0x0`
	`l.addi r4,r0,0x0`
	`l.addi r5,r0,0x0`
	`l.addi r6,r0,0x0`
	`l.addi r7,r0,0x0`
	`l.addi r8,r0,0x0`
	`l.addi r9,r0,0x0`
	`l.addi r10,r0,0x0`
	`l.addi r11,r0,0x0`
	`l.addi r12,r0,0x0`
	`l.addi r13,r0,0x0`
	`l.addi r14,r0,0x0`
	`l.addi r15,r0,0x0`
	`l.addi r16,r0,0x0`
	`l.addi r17,r0,0x0`
	`l.addi r18,r0,0x0`
	`l.addi r19,r0,0x0`
	`l.addi r20,r0,0x0`
	`l.addi r21,r0,0x0`
	`l.addi r22,r0,0x0`
	`l.addi r23,r0,0x0`
	`l.addi r24,r0,0x0`
	`l.addi r25,r0,0x0`
	`l.addi r26,r0,0x0`
	`l.addi r27,r0,0x0`
	`l.addi r28,r0,0x0`
	`l.addi r29,r0,0x0`
	`l.addi r30,r0,0x0`
	`l.addi r31,r0,0x0`

	`l.movhi r3,hi(start)`
	`l.ori r3,r3,lo(start)`
	`l.jr r3`
	`l.nop`


	`.org 0x200`
`buserr_vector:`	`buserr_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 92...	Line 131...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x300`
`dpfault_vector:`	`dpfault_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 110...	Line 150...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x400`
`ipfault_vector:`	`ipfault_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 128...	Line 169...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x500`
`tick_vector:`	`tick_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 146...	Line 188...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x600`
`align_vector:`	`align_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 164...	Line 207...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x700`
`illinsn_vector:`	`illinsn_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 182...	Line 226...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x800`
`int_vector:`	`int_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 200...	Line 245...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0x900`
`dtlbmiss_vector:`	`dtlbmiss_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 218...	Line 264...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0xa00`
`itlbmiss_vector:`	`itlbmiss_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 236...	Line 283...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0xb00`
`range_vector:`	`range_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 254...	Line 302...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0xc00`
`syscall_vector:`	`syscall_vector:`
`l.addi r3,r3,4`	`l.addi r3,r3,4`

`l.mfspr r4,r0,SPR_SR`	`l.mfspr r4,r0,SPR_SR`
`l.andi r4,r4,7`	`l.andi r4,r4,7`
Line 277...	Line 326...
`l.mtspr r0,r4,SPR_EPCR_BASE`	`l.mtspr r0,r4,SPR_EPCR_BASE`

`l.rfe`	`l.rfe`
`l.addi r3,r3,8`	`l.addi r3,r3,8`

	`.org 0xd00`
`break_vector:`	`break_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 295...	Line 345...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`.org 0xe00`
`trap_vector:`	`trap_vector:`
`l.addi r1,r1,-120`	`l.addi r1,r1,-120`
`l.sw 0x1c(r1),r9`	`l.sw 0x1c(r1),r9`
`l.sw 0x20(r1),r10`	`l.sw 0x20(r1),r10`
`l.movhi r9,hi(store_regs)`	`l.movhi r9,hi(store_regs)`
Line 313...	Line 364...
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

`/* Our special text section is used to guarantee this code goes first`
`when linking. */`
`.section .except-text`

`.org 0x100`	`.section .text`
`reset_vector:`
`l.nop`
`l.nop`
`l.addi r2,r0,0x0`
`l.addi r3,r0,0x0`
`l.addi r4,r0,0x0`
`l.addi r5,r0,0x0`
`l.addi r6,r0,0x0`
`l.addi r7,r0,0x0`
`l.addi r8,r0,0x0`
`l.addi r9,r0,0x0`
`l.addi r10,r0,0x0`
`l.addi r11,r0,0x0`
`l.addi r12,r0,0x0`
`l.addi r13,r0,0x0`
`l.addi r14,r0,0x0`
`l.addi r15,r0,0x0`
`l.addi r16,r0,0x0`
`l.addi r17,r0,0x0`
`l.addi r18,r0,0x0`
`l.addi r19,r0,0x0`
`l.addi r20,r0,0x0`
`l.addi r21,r0,0x0`
`l.addi r22,r0,0x0`
`l.addi r23,r0,0x0`
`l.addi r24,r0,0x0`
`l.addi r25,r0,0x0`
`l.addi r26,r0,0x0`
`l.addi r27,r0,0x0`
`l.addi r28,r0,0x0`
`l.addi r29,r0,0x0`
`l.addi r30,r0,0x0`
`l.addi r31,r0,0x0`

`l.movhi r3,hi(start)`
`l.ori r3,r3,lo(start)`
`l.jr r3`
`l.nop`
`start:`	`start:`
`l.jal init_mc`
`l.nop`

`l.movhi r1,hi(stack)`	`l.movhi r1,hi(stack)`
`l.ori r1,r1,lo(stack)`	`l.ori r1,r1,lo(stack)`
	`l.ori r2,r1,0`

`/* Setup exception wrappers */`	`bss_clear:`
`l.movhi r3,hi(_src_beg)`	`/* Clear BSS */`
`l.ori r3,r3,lo(_src_beg)`	`l.movhi r3, hi(_bstart)`
`l.addi r7,r0,0x100`	`l.ori r3, r3, lo(_bstart)`
	`l.movhi r4, hi(_bend)`
`1: l.addi r7,r7,0x100`	`l.ori r4, r4, lo(_bend)`
`l.sfeqi r7,0xf00`	`bss_clear_loop:`
`l.bf 1f`	`l.sw 0(r3), r0`
`l.nop`	`l.sfgtu r3, r4`
`l.addi r4,r7,0`	`l.bnf bss_clear_loop`
`l.addi r5,r0,0`
`2:`
`l.lwz r6,0(r3)`
`l.sw 0(r4),r6`
`l.addi r3,r3,4`
`l.addi r4,r4,4`
`l.addi r5,r5,1`
`l.sfeqi r5,16`
`l.bf 1b`
`l.nop`
`l.j 2b`
`l.nop`
`1:`
`/* Copy data section */`
`l.movhi r4,hi(_dst_beg)`
`l.ori r4,r4,lo(_dst_beg)`
`l.movhi r5,hi(_dst_end)`
`l.ori r5,r5,lo(_dst_end)`
`l.sub r5,r5,r4`
`l.sfeqi r5,0`
`l.bf 2f`
`l.nop`
`1: l.lwz r6,0(r3)`
`l.sw 0(r4),r6`
`l.addi r3,r3,4`	`l.addi r3,r3,4`
`l.addi r4,r4,4`
`l.addi r5,r5,-4`
`l.sfgtsi r5,0`
`l.bf 1b`
`l.nop`

`2:`

`l.movhi r2,hi(reset)`
`l.ori r2,r2,lo(reset)`
`l.jr r2`
`l.nop`

`init_mc:`

`l.movhi r3,hi(MC_BASE_ADDR)`
`l.ori r3,r3,lo(MC_BASE_ADDR)`

`l.addi r4,r3,MC_CSC(0)`
`l.movhi r5,hi(FLASH_BASE_ADDR)`
`l.srai r5,r5,6`
`l.ori r5,r5,0x0025`
`l.sw 0(r4),r5`

`l.addi r4,r3,MC_TMS(0)`
`l.movhi r5,hi(FLASH_TMS_VAL)`
`l.ori r5,r5,lo(FLASH_TMS_VAL)`
`l.sw 0(r4),r5`

`l.addi r4,r3,MC_BA_MASK`
`l.addi r5,r0,MC_MASK_VAL`
`l.sw 0(r4),r5`

`l.addi r4,r3,MC_CSR`
`l.movhi r5,hi(MC_CSR_VAL)`
`l.ori r5,r5,lo(MC_CSR_VAL)`
`l.sw 0(r4),r5`

`l.addi r4,r3,MC_TMS(1)`
`l.movhi r5,hi(SDRAM_TMS_VAL)`
`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
`l.sw 0(r4),r5`

`l.addi r4,r3,MC_CSC(1)`
`l.movhi r5,hi(SDRAM_BASE_ADDR)`
`l.srai r5,r5,6`
`l.ori r5,r5,0x0411`
`l.sw 0(r4),r5`

`l.jr r9`
	`l.movhi r3,hi(reset)`
	`l.ori r3,r3,lo(reset)`
	`l.jr r3`
`l.nop`	`l.nop`

`store_regs:`	`store_regs:`
`l.sw 0x00(r1),r2`	`l.sw 0x00(r1),r2`
`l.sw 0x04(r1),r3`	`l.sw 0x04(r1),r3`
Line 533...	Line 474...
`l.addi r1,r1,120`	`l.addi r1,r1,120`
`l.mtspr r0,r9,SPR_EPCR_BASE`	`l.mtspr r0,r9,SPR_EPCR_BASE`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`

`.section .text`

`except_basic:`	`except_basic:`
`sys1:`	`sys1:`
`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`	`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
`l.mfspr r4,r0,SPR_SR`	`l.mfspr r4,r0,SPR_SR`
`l.and r4,r4,r3`	`l.and r4,r4,r3`
Line 640...	Line 579...
`l.lwz r11,0(r4)`	`l.lwz r11,0(r4)`

`b_trap:`	`b_trap:`
`l.jr r9`	`l.jr r9`
`trap:`	`trap:`
`l.trap 1`	`l.trap 15`
`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`b_range:`	`b_range:`
`l.jr r9`	`l.jr r9`
Line 666...	Line 605...

`jump_back:`	`jump_back:`
`l.addi r11,r0,0`	`l.addi r11,r0,0`
`l.jr r9`	`l.jr r9`
`l.addi r11,r11,1`	`l.addi r11,r11,1`

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except-test/] [except-test-s.S] - Diff between revs 346 and 458