| Line 30... |
Line 30... |
#include "int.h"
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#include "int.h"
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/* Define RAM physical location and size
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/* Define RAM physical location and size
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Bottom half will be used for this program, the rest
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Bottom half will be used for this program, the rest
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will be used for testing */
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will be used for testing */
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#define FLASH_START 0xf0000000
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#define FLASH_SIZE 0x00200000
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#define RAM_START 0x00000000
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#define RAM_START 0x00000000
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#define RAM_SIZE 0x04000000
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#define RAM_SIZE 0x00200000
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#define TEST_BASE 0xa5000000
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/* MMU page size */
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/* MMU page size */
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#define PAGE_SIZE 8192
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#define PAGE_SIZE 8192
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/* Number of DTLB sets used (power of 2, max is 256) */
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/* Number of DTLB sets used (power of 2, max is 256) */
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| Line 57... |
Line 53... |
/* TLB mode codes */
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/* TLB mode codes */
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#define TLB_CODE_ONE_TO_ONE 0x00000000
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#define TLB_CODE_ONE_TO_ONE 0x00000000
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#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
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#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
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#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
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#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
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#define TLB_TEXT_SET_NB 6
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#define TLB_TEXT_SET_NB 8
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#define TLB_DATA_SET_NB 2
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#define TLB_DATA_SET_NB 8
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#define TLB_CODE_MASK 0xfffff000
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#define TLB_CODE_MASK 0xfffff000
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#define TLB_PR_MASK 0x00000fff
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#define TLB_PR_MASK 0x00000fff
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \
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SPR_DTLBTR_URE | \
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SPR_DTLBTR_URE | \
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| Line 437... |
Line 433... |
}
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}
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}
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}
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/* Set one to one translation for the use of this program */
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/* Set one to one translation for the use of this program */
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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ea = FLASH_START + (i*PAGE_SIZE);
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ea = RAM_START + (i*PAGE_SIZE);
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ta = FLASH_START + (i*PAGE_SIZE);
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ta = RAM_START + (i*PAGE_SIZE);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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}
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}
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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| Line 625... |
Line 621... |
}
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}
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}
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}
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/* Set one to one translation for the use of this program */
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/* Set one to one translation for the use of this program */
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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ea = FLASH_START + (i*PAGE_SIZE);
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ea = RAM_START + (i*PAGE_SIZE);
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ta = FLASH_START + (i*PAGE_SIZE);
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ta = RAM_START + (i*PAGE_SIZE);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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}
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}
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/* Invalidate all entries in DTLB */
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/* Invalidate all entries in DTLB */
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| Line 656... |
Line 652... |
except_ea = 0;
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except_ea = 0;
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/* Set IMMU translation */
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/* Set IMMU translation */
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ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
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ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
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mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) |
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mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, ((ea + PAGE_SIZE) & SPR_ITLBTR_PPN) | itlb_val);
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SPR_ITLBMR_V);
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// Set translate to invalid address: 0xee000000
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mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, (0xee000000 & SPR_ITLBTR_PPN) |
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itlb_val);
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/* Enable IMMU */
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/* Enable IMMU */
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immu_enable ();
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immu_enable ();
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/* Check if there was bus error exception */
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/* Check if there was bus error exception */
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| Line 678... |
Line 677... |
except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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/* Copy jump instruction to last location of RAM */
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/* Set EA as an invalid memory location */
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ea = RAM_START + RAM_SIZE - 8;
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ea = 0xee000000;
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memcpy((void *)ea, (void *)&jump_back, 8);
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/* Check if there was bus error exception */
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/* Check if there was bus error exception */
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ret = call (ea, 0);
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ret = call (ea, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_pc == ea + 4);
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ASSERT(except_pc == ea);
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ASSERT(except_ea == ea + 8);
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ASSERT(except_ea == ea);
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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/* Set DMMU translation */
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/* Set DMMU translation */
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ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
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ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
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dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
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dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
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mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) |
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mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ((ea + PAGE_SIZE) & SPR_DTLBTR_PPN) | dtlb_val);
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SPR_DTLBMR_V);
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// Set translate to invalid address: 0xee000000
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mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, (0xee000000 & SPR_DTLBTR_PPN) |
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dtlb_val);
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/* Enable DMMU */
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/* Enable DMMU */
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dmmu_enable ();
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dmmu_enable ();
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/* Check if there was bus error exception */
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/* Check if there was bus error exception */
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Line 722... |
except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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// Set ea to invalid address
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ea = 0xee000000;
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/* Check if there was bus error exception */
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/* Check if there was bus error exception */
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ret = call ((unsigned long)&load_acc_32, ea );
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ret = call ((unsigned long)&load_acc_32, ea );
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
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ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
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| Line 751... |
Line 755... |
rather than the immediately preceding l.jr r9 (allowing us to
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rather than the immediately preceding l.jr r9 (allowing us to
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recover). Secondly it used 0xffffffff as an illegal instruction. Except
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recover). Secondly it used 0xffffffff as an illegal instruction. Except
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it isn't - it's l.cust8 0x3ffffff.
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it isn't - it's l.cust8 0x3ffffff.
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Fixed by a) jumping to the correct location and b) really using an
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Fixed by a) jumping to the correct location and b) really using an
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illegal instruction. */
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illegal instruction (opcode 0x3a. */
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REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
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REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
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REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe5dfffff;
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REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe8000000;
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/* Check if there was illegal insn exception. Note that if an illegal
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/* Check if there was illegal insn exception. Note that if an illegal
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instruction occurs in a delay slot (like this one), then the exception
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instruction occurs in a delay slot (like this one), then the exception
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PC is the address of the hump instruction. */
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PC is the address of the jump instruction. */
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ret = call (RAM_START + (RAM_SIZE/2), 0 ); /* JPB */
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ret = call (RAM_START + (RAM_SIZE/2), 0 ); /* JPB */
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_ILLINSN));
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ASSERT(except_mask == (1 << V_ILLINSN));
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ASSERT(except_pc == (RAM_START + (RAM_SIZE/2)));
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ASSERT(except_pc == (RAM_START + (RAM_SIZE/2)));
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| Line 911... |
Line 915... |
}
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}
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}
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}
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/* Set one to one translation for the use of this program */
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/* Set one to one translation for the use of this program */
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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for (i = 0; i < TLB_TEXT_SET_NB; i++) {
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ea = FLASH_START + (i*PAGE_SIZE);
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ea = RAM_START + (i*PAGE_SIZE);
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ta = FLASH_START + (i*PAGE_SIZE);
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ta = RAM_START + (i*PAGE_SIZE);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
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}
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}
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/* Set dtlb no permisions */
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/* Set dtlb no permisions */
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| Line 951... |
Line 955... |
except_ea = 0;
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except_ea = 0;
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/* Enable IMMU */
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/* Enable IMMU */
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immu_enable ();
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immu_enable ();
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/* The following is currently disabled due to differing behavior between
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or1ksim and the OR1200 RTL. Or1ksim appears to receive only 1 exception
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during the call_with_int() call. The OR1200 correctly, in my opionion,
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reports 2 exceptions - ITLB miss and tick timer. -- Julius
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TODO: Investigate why or1ksim isn't reporting ITLB miss.
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*/
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#if 0
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/* Check if there was INT exception */
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/* Check if there was INT exception */
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call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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ASSERT(except_count == 1);
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printf("ec:%d 0x%lx\n",except_count,except_mask); ASSERT(except_count == 2);
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ASSERT(except_mask == (1 << V_TICK));
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ASSERT(except_mask == ((1 << V_TICK) | (1 << V_ITLB_MISS)));
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printf("epc %8lx\n",except_pc);
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ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
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ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
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/* Reset except counter */
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/* Reset except counter */
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except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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#endif
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/* Check if there was ITLB exception */
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/* Check if there was ITLB exception */
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call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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ASSERT(except_mask == (1 << V_ITLB_MISS));
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| Line 992... |
Line 1008... |
except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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/* Check if there was bus error exception */
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call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
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ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
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/* Reset except counter */
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except_count = 0;
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except_mask = 0;
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except_pc = 0;
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except_ea = 0;
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/* Disable MMU */
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/* Disable MMU */
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immu_disable ();
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immu_disable ();
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/* Set illegal instruction. JPB. Use a really illegal instruction, not
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/* Set illegal instruction. JPB. Use a really illegal instruction, not
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l.cust8 0x3ffffff. */
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l.cust8 0x3ffffff. */
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REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 0) = 0x00000000;
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REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 0) = 0x00000000;
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REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xe5dfffff;
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REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xe8000000;
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REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 8) = 0x00000000;
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REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 8) = 0x00000000;
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/* Check if there was illegal insn exception */
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/* Check if there was illegal insn exception */
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call (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4, 0);
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call (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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| Line 1075... |
Line 1078... |
except_count = 0;
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except_count = 0;
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except_mask = 0;
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except_mask = 0;
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except_pc = 0;
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except_pc = 0;
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except_ea = 0;
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except_ea = 0;
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/* Check if there was bus error exception */
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ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_BERR));
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ASSERT(ret == 0x12345678);
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ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
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ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
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/* Reset except counter */
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except_count = 0;
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except_mask = 0;
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except_pc = 0;
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except_ea = 0;
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/* Check if there was trap exception */
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/* Check if there was trap exception */
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call ((unsigned long)&trap, 0);
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call ((unsigned long)&trap, 0);
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ASSERT(except_count == 1);
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ASSERT(except_count == 1);
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ASSERT(except_mask == (1 << V_TRAP));
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ASSERT(except_mask == (1 << V_TRAP));
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ASSERT(except_pc == (unsigned long)(trap));
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ASSERT(except_pc == (unsigned long)(trap));
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| Line 1139... |
Line 1128... |
excpt_range = (unsigned long)range_handler;
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excpt_range = (unsigned long)range_handler;
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/* Exception basic test */
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/* Exception basic test */
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ret = except_basic ();
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ret = except_basic ();
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ASSERT(ret == 0);
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ASSERT(ret == 0);
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printf("interupt_test\n");
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/* Interrupt exception test */
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/* Interrupt exception test */
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interrupt_test ();
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interrupt_test ();
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printf("itlb_test\n");
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/* ITLB exception test */
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/* ITLB exception test */
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itlb_test ();
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itlb_test ();
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printf("dtlb_test\n");
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printf("dtlb_test\n");
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/* DTLB exception test */
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/* DTLB exception test */
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