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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [ext/] [ext.S] - Diff between revs 458 and 787

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Rev 458 Rev 787
Line 119... Line 119...
        l.bf    ext_fail; \
        l.bf    ext_fail; \
        l.nop;
        l.nop;
 
 
        .section .text
        .section .text
start_test:
start_test:
 
    // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
 
    // and indeed it is not when simulating the or1200 Verilog core.
 
    l.andi  r0,r0,0x0
 
 
        /* Test l.extbs */
        /* Test l.extbs */
        CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
        CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
        CHECK_HIGH3_CLEAR(l.extbs, 0x53)
        CHECK_HIGH3_CLEAR(l.extbs, 0x53)
        CHECK_HIGH3_CLEAR(l.extbs, 0xff53)
        CHECK_HIGH3_CLEAR(l.extbs, 0xff53)
        CHECK_HIGH3_CLEAR(l.extbs, 0x1234)
        CHECK_HIGH3_CLEAR(l.extbs, 0x1234)

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