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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [flag/] [flag.S] - Diff between revs 458 and 787

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Rev 458 Rev 787
Line 34... Line 34...
        .section .except, "ax"
        .section .except, "ax"
 
 
        .org 0x100
        .org 0x100
_reset:
_reset:
        l.nop
        l.nop
 
 
 
    // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
 
    // and indeed it is not when simulating the or1200 Verilog core.
 
    l.andi  r0,r0,0x0
 
 
        l.movhi r10,0x8000
        l.movhi r10,0x8000
        l.addi  r11,r0,-1
        l.addi  r11,r0,-1
        l.addi  r12,r0,2
        l.addi  r12,r0,2
        l.addi  r13,r0,0x5678
        l.addi  r13,r0,0x5678
        l.movhi r14,0xdead
        l.movhi r14,0xdead

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