| Line 26... |
Line 26... |
--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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|
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/* Support file for c based tests */
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/* Support file for c based tests */
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#include "spr-defs.h"
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#include "spr-defs.h"
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|
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#define reset _reset
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#define reset reset
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|
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.section .stack
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.section .stack
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.space 0x1000
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.space 0x1000
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_stack:
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stack:
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|
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.extern _reset_support
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.extern reset_support
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.extern _c_reset
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.extern c_reset
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.extern _excpt_buserr
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.extern excpt_buserr
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.extern _excpt_dpfault
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.extern excpt_dpfault
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.extern _excpt_ipfault
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.extern excpt_ipfault
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.extern _excpt_tick
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.extern excpt_tick
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.extern _excpt_align
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.extern excpt_align
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.extern _excpt_illinsn
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.extern excpt_illinsn
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.extern _excpt_int
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.extern excpt_int
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.extern _excpt_dtlbmiss
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.extern excpt_dtlbmiss
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.extern _excpt_itlbmiss
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.extern excpt_itlbmiss
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.extern _excpt_range
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.extern excpt_range
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.extern _excpt_syscall
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.extern excpt_syscall
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.extern _excpt_break
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.extern excpt_break
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.extern _excpt_trap
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.extern excpt_trap
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|
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.section .except,"ax"
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.section .except,"ax"
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.org 0x100
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.org 0x100
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_reset_vector:
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reset_vector:
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l.nop
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l.nop
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l.nop
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l.nop
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l.addi r4,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r6,r0,0x0
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| Line 85... |
Line 85... |
l.addi r31,r0,0x0
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l.addi r31,r0,0x0
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|
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l.j init_mc
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l.j init_mc
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l.nop
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l.nop
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|
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start: l.movhi r1,hi(_stack)
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start: l.movhi r1,hi(stack)
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l.ori r1,r1,lo(_stack)
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l.ori r1,r1,lo(stack)
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|
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/* Check if this is RTL version */
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/* Check if this is RTL version */
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l.lbz r3,0(r0)
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l.lbz r3,0(r0)
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l.sfeqi r3,0xff
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l.sfeqi r3,0xff
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l.bf 2f
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l.bf 2f
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| Line 119... |
Line 119... |
l.ori r2,r2,lo(reset)
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l.ori r2,r2,lo(reset)
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l.jr r2
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l.jr r2
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l.nop
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l.nop
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|
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.org 0x200
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.org 0x200
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_buserr_vector:
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buserr_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_buserr)
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l.movhi r10,hi(excpt_buserr)
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l.ori r10,r10,lo(_excpt_buserr)
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l.ori r10,r10,lo(excpt_buserr)
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l.lwz r10,0x0(r10)
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l.lwz r10,0x0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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|
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.org 0x300
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.org 0x300
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_dpfault_vector:
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dpfault_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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| Line 145... |
Line 145... |
l.addi r3,r3,-4
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l.addi r3,r3,-4
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l.mtspr r0,r3,SPR_EPCR_BASE
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l.mtspr r0,r3,SPR_EPCR_BASE
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|
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_dpfault)
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l.movhi r10,hi(excpt_dpfault)
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l.ori r10,r10,lo(_excpt_dpfault)
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l.ori r10,r10,lo(excpt_dpfault)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0x400
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.org 0x400
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_ipfault_vector:
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ipfault_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_ipfault)
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l.movhi r10,hi(excpt_ipfault)
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l.ori r10,r10,lo(_excpt_ipfault)
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l.ori r10,r10,lo(excpt_ipfault)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0x500
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.org 0x500
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_lpint_vector:
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lpint_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_tick)
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l.movhi r10,hi(excpt_tick)
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l.ori r10,r10,lo(_excpt_tick)
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l.ori r10,r10,lo(excpt_tick)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0x600
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.org 0x600
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_align_vector:
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align_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_align)
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l.movhi r10,hi(excpt_align)
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l.ori r10,r10,lo(_excpt_align)
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l.ori r10,r10,lo(excpt_align)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0x700
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.org 0x700
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_illinsn_vector:
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illinsn_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_illinsn)
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l.movhi r10,hi(excpt_illinsn)
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l.ori r10,r10,lo(_excpt_illinsn)
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l.ori r10,r10,lo(excpt_illinsn)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0x800
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.org 0x800
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_hpint_vector:
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hpint_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_int)
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l.movhi r10,hi(excpt_int)
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l.ori r10,r10,lo(_excpt_int)
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l.ori r10,r10,lo(excpt_int)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0x900
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.org 0x900
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_dtlbmiss_vector:
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dtlbmiss_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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| Line 234... |
Line 234... |
l.addi r3,r3,-4
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l.addi r3,r3,-4
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l.mtspr r0,r3,SPR_EPCR_BASE
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l.mtspr r0,r3,SPR_EPCR_BASE
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_dtlbmiss)
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l.movhi r10,hi(excpt_dtlbmiss)
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l.ori r10,r10,lo(_excpt_dtlbmiss)
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l.ori r10,r10,lo(excpt_dtlbmiss)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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.org 0xa00
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.org 0xa00
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_itlbmiss_vector:
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itlbmiss_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_itlbmiss)
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l.movhi r10,hi(excpt_itlbmiss)
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l.ori r10,r10,lo(_excpt_itlbmiss)
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l.ori r10,r10,lo(excpt_itlbmiss)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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|
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.org 0xb00
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.org 0xb00
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_range_vector:
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range_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_range)
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l.movhi r10,hi(excpt_range)
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l.ori r10,r10,lo(_excpt_range)
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l.ori r10,r10,lo(excpt_range)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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|
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.org 0xc00
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.org 0xc00
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_syscall_vector:
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syscall_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_syscall)
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l.movhi r10,hi(excpt_syscall)
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l.ori r10,r10,lo(_excpt_syscall)
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l.ori r10,r10,lo(excpt_syscall)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
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|
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.org 0xd00
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.org 0xd00
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_break_vector:
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break_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
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l.nop
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l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_break)
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l.movhi r10,hi(excpt_break)
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l.ori r10,r10,lo(_excpt_break)
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l.ori r10,r10,lo(excpt_break)
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l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
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l.nop
|
|
|
.org 0xe00
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.org 0xe00
|
_trap_vector:
|
trap_vector:
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l.addi r1,r1,-116
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l.addi r1,r1,-116
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l.sw 0x18(r1),r9
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l.sw 0x18(r1),r9
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l.jal store_regs
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l.jal store_regs
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l.nop
|
l.nop
|
l.movhi r9,hi(end_except)
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l.movhi r9,hi(end_except)
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l.ori r9,r9,lo(end_except)
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l.ori r9,r9,lo(end_except)
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l.movhi r10,hi(_excpt_trap)
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l.movhi r10,hi(excpt_trap)
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l.ori r10,r10,lo(_excpt_trap)
|
l.ori r10,r10,lo(excpt_trap)
|
l.lwz r10,0(r10)
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l.lwz r10,0(r10)
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l.jr r10
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l.jr r10
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l.nop
|
l.nop
|
|
|
store_regs:
|
store_regs:
|
