URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mc-common/] [except-mc.S] - Diff between revs 346 and 787

Rev 346	Rev 787
Line 53...	Line 53...
`.section .except,"ax"`	`.section .except,"ax"`
`.org 0x100`	`.org 0x100`
`reset_vector:`	`reset_vector:`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

	`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
	`// and indeed it is not when simulating the or1200 Verilog core.`
	`l.andi r0,r0,0x0`

`l.addi r4,r0,0x0`	`l.addi r4,r0,0x0`
`l.addi r5,r0,0x0`	`l.addi r5,r0,0x0`
`l.addi r6,r0,0x0`	`l.addi r6,r0,0x0`
`l.addi r7,r0,0x0`	`l.addi r7,r0,0x0`
`l.addi r8,r0,0x0`	`l.addi r8,r0,0x0`