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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mmu/] [mmu-asm.S] - Diff between revs 90 and 346

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Rev 90	Rev 346
Line 31...	Line 31...
`SPR_DTLBTR_UWE \| \`	`SPR_DTLBTR_UWE \| \`
`SPR_DTLBTR_SRE \| \`	`SPR_DTLBTR_SRE \| \`
`SPR_DTLBTR_SWE )`	`SPR_DTLBTR_SWE )`
`#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE \| \`	`#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE \| \`
`SPR_ITLBTR_UXE )`	`SPR_ITLBTR_UXE )`
`.global _lo_dmmu_en`	`.global lo_dmmu_en`
`.global _lo_immu_en`	`.global lo_immu_en`
`.global _lo_dtlb_ci_test`	`.global lo_dtlb_ci_test`
`.global _lo_itlb_ci_test`	`.global lo_itlb_ci_test`
`.global _testjump`	`.global testjump`
`.global _ic_enable`	`.global ic_enable`
`.global _ic_disable`	`.global ic_disable`
`.global _dc_enable`	`.global dc_enable`
`.global _dc_disable`	`.global dc_disable`

`_lo_dmmu_en:`	`lo_dmmu_en:`
`l.mfspr r11,r0,SPR_SR`	`l.mfspr r11,r0,SPR_SR`
`l.ori r11,r11,SPR_SR_DME`	`l.ori r11,r11,SPR_SR_DME`
`l.mtspr r0,r11,SPR_ESR_BASE`	`l.mtspr r0,r11,SPR_ESR_BASE`
`l.mtspr r0,r9,SPR_EPCR_BASE`	`l.mtspr r0,r9,SPR_EPCR_BASE`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`

`_lo_dmmu_dis:`	`lo_dmmu_dis:`
`l.addi r13,r0,-1`	`l.addi r13,r0,-1`
`l.xori r13,r13,SPR_SR_DME`	`l.xori r13,r13,SPR_SR_DME`
`l.mfspr r11,r0,SPR_SR`	`l.mfspr r11,r0,SPR_SR`
`l.and r11,r11,r13`	`l.and r11,r11,r13`
`l.mtspr r0,r11,SPR_SR`	`l.mtspr r0,r11,SPR_SR`
`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_lo_immu_en:`	`lo_immu_en:`
`l.mfspr r11,r0,SPR_SR`	`l.mfspr r11,r0,SPR_SR`
`l.ori r11,r11,SPR_SR_IME`	`l.ori r11,r11,SPR_SR_IME`
`l.mtspr r0,r11,SPR_ESR_BASE`	`l.mtspr r0,r11,SPR_ESR_BASE`
`l.mtspr r0,r9,SPR_EPCR_BASE`	`l.mtspr r0,r9,SPR_EPCR_BASE`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`

`_lo_immu_dis:`	`lo_immu_dis:`
`l.addi r13,r0,-1`	`l.addi r13,r0,-1`
`l.xori r13,r13,SPR_SR_IME`	`l.xori r13,r13,SPR_SR_IME`
`l.mfspr r11,r0,SPR_SR`	`l.mfspr r11,r0,SPR_SR`
`l.and r11,r11,r13`	`l.and r11,r11,r13`
`l.mtspr r0,r11,SPR_SR`	`l.mtspr r0,r11,SPR_SR`
`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_testjump:`	`testjump:`
`l.movhi r5,0x4800`	`l.movhi r5,0x4800`
`l.ori r5,r5,0x4800`	`l.ori r5,r5,0x4800`
`l.sw 0x0(r3),r5`	`l.sw 0x0(r3),r5`
`l.movhi r5,0x1500`	`l.movhi r5,0x1500`
`l.ori r5,r5,0x0000`	`l.ori r5,r5,0x0000`
Line 89...	Line 89...
`l.nop`	`l.nop`
`l.or r9,r0,r5`	`l.or r9,r0,r5`
`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_ic_enable:`	`ic_enable:`
`/* Disable IC */`	`/* Disable IC */`
`l.mfspr r13,r0,SPR_SR`	`l.mfspr r13,r0,SPR_SR`
`l.addi r11,r0,-1`	`l.addi r11,r0,-1`
`l.xori r11,r11,SPR_SR_ICE`	`l.xori r11,r11,SPR_SR_ICE`
`l.and r11,r13,r11`	`l.and r11,r13,r11`
Line 119...	Line 119...
`l.nop`	`l.nop`

`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_ic_disable:`	`ic_disable:`
`/* Disable IC */`	`/* Disable IC */`
`l.mfspr r13,r0,SPR_SR`	`l.mfspr r13,r0,SPR_SR`
`l.addi r11,r0,-1`	`l.addi r11,r0,-1`
`l.xori r11,r11,SPR_SR_ICE`	`l.xori r11,r11,SPR_SR_ICE`
`l.and r11,r13,r11`	`l.and r11,r13,r11`
`l.mtspr r0,r11,SPR_SR`	`l.mtspr r0,r11,SPR_SR`

`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_dc_enable:`	`dc_enable:`
`/* Disable DC */`	`/* Disable DC */`
`l.mfspr r13,r0,SPR_SR`	`l.mfspr r13,r0,SPR_SR`
`l.addi r11,r0,-1`	`l.addi r11,r0,-1`
`l.xori r11,r11,SPR_SR_DCE`	`l.xori r11,r11,SPR_SR_DCE`
`l.and r11,r13,r11`	`l.and r11,r13,r11`
Line 155...	Line 155...
`l.mtspr r0,r13,SPR_SR`	`l.mtspr r0,r13,SPR_SR`

`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_dc_disable:`	`dc_disable:`
`/* Disable DC */`	`/* Disable DC */`
`l.mfspr r13,r0,SPR_SR`	`l.mfspr r13,r0,SPR_SR`
`l.addi r11,r0,-1`	`l.addi r11,r0,-1`
`l.xori r11,r11,SPR_SR_DCE`	`l.xori r11,r11,SPR_SR_DCE`
`l.and r11,r13,r11`	`l.and r11,r13,r11`
Line 167...	Line 167...

`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`/* dtlb_ic_test(unsigned long add, unsigned long set) */`	`/* dtlb_ic_test(unsigned long add, unsigned long set) */`
`_lo_dtlb_ci_test:`	`lo_dtlb_ci_test:`
`l.addi r1,r1,-4`	`l.addi r1,r1,-4`
`l.sw 0(r1),r9`	`l.sw 0(r1),r9`

`l.addi r8,r0,0`	`l.addi r8,r0,0`

Line 196...	Line 196...
`l.addi r5,r3,PAGE_SIZE`	`l.addi r5,r3,PAGE_SIZE`
`l.ori r5,r5,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`	`l.ori r5,r5,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
`l.addi r6,r4,1`	`l.addi r6,r4,1`
`l.mtspr r6,r5,SPR_DTLBTR_BASE(0)`	`l.mtspr r6,r5,SPR_DTLBTR_BASE(0)`

`l.jal _lo_dmmu_en`	`l.jal lo_dmmu_en`
`l.nop`	`l.nop`
`l.jal _dc_enable`	`l.jal dc_enable`
`l.nop`	`l.nop`

`l.movhi r6,hi(0x01234567)`	`l.movhi r6,hi(0x01234567)`
`l.ori r6,r6,lo(0x01234567)`	`l.ori r6,r6,lo(0x01234567)`
`l.lwz r5,0(r3)`	`l.lwz r5,0(r3)`
Line 221...	Line 221...
`l.sw 0(r3),r5`	`l.sw 0(r3),r5`
`l.movhi r5,hi(0xfedcba9)`	`l.movhi r5,hi(0xfedcba9)`
`l.ori r5,r5,lo(0xfedcba9)`	`l.ori r5,r5,lo(0xfedcba9)`
`l.sw (PAGE_SIZE - 4)(r3),r5`	`l.sw (PAGE_SIZE - 4)(r3),r5`

`l.jal _lo_dmmu_dis`	`l.jal lo_dmmu_dis`
`l.nop`	`l.nop`
`l.ori r5,r3,(DTLB_PR_NOLIMIT)`	`l.ori r5,r3,(DTLB_PR_NOLIMIT)`
`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`	`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
`l.jal _lo_dmmu_en`	`l.jal lo_dmmu_en`
`l.nop`	`l.nop`

`l.movhi r6,hi(0x76543210)`	`l.movhi r6,hi(0x76543210)`
`l.ori r6,r6,lo(0x76543210)`	`l.ori r6,r6,lo(0x76543210)`
`l.lwz r5,0(r3)`	`l.lwz r5,0(r3)`
Line 241...	Line 241...
`l.lwz r5,(PAGE_SIZE - 4)(r3)`	`l.lwz r5,(PAGE_SIZE - 4)(r3)`
`l.sfeq r6,r5`	`l.sfeq r6,r5`
`l.bnf 14f`	`l.bnf 14f`
`l.nop`	`l.nop`

`l.jal _lo_dmmu_dis`	`l.jal lo_dmmu_dis`
`l.nop`	`l.nop`
`l.ori r5,r3,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`	`l.ori r5,r3,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`	`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
`l.jal _lo_dmmu_en`	`l.jal lo_dmmu_en`
`l.nop`	`l.nop`

`l.movhi r5,hi(0x00112233)`	`l.movhi r5,hi(0x00112233)`
`l.ori r5,r5,lo(0x00112233)`	`l.ori r5,r5,lo(0x00112233)`
`l.sw 0(r3),r5`	`l.sw 0(r3),r5`
Line 279...	Line 279...
`l.lwz r5,(PAGE_SIZE - 4)(r3)`	`l.lwz r5,(PAGE_SIZE - 4)(r3)`
`l.sfeq r6,r5`	`l.sfeq r6,r5`
`l.bnf 16f`	`l.bnf 16f`
`l.nop`	`l.nop`

`l.jal _lo_dmmu_dis`	`l.jal lo_dmmu_dis`
`l.nop`	`l.nop`
`l.ori r5,r3,(DTLB_PR_NOLIMIT)`	`l.ori r5,r3,(DTLB_PR_NOLIMIT)`
`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`	`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
`l.jal _lo_dmmu_en`	`l.jal lo_dmmu_en`
`l.nop`	`l.nop`

`l.movhi r6,hi(0x76543210)`	`l.movhi r6,hi(0x76543210)`
`l.ori r6,r6,lo(0x76543210)`	`l.ori r6,r6,lo(0x76543210)`
`l.lwz r5,0(r3)`	`l.lwz r5,0(r3)`
Line 301...	Line 301...
`l.sfeq r6,r5`	`l.sfeq r6,r5`
`l.bnf 18f`	`l.bnf 18f`
`l.nop`	`l.nop`

`/* Invalidate cache */`	`/* Invalidate cache */`
`l.jal _dc_disable`	`l.jal dc_disable`
`l.nop`	`l.nop`

`l.movhi r5,hi(0x00112233)`	`l.movhi r5,hi(0x00112233)`
`l.ori r5,r5,lo(0x00112233)`	`l.ori r5,r5,lo(0x00112233)`
`l.sw 12(r3),r5`	`l.sw 12(r3),r5`
Line 320...	Line 320...
`l.sw 0(r3),r5`	`l.sw 0(r3),r5`
`l.movhi r5,hi(0x44556677)`	`l.movhi r5,hi(0x44556677)`
`l.ori r5,r5,lo(0x44556677)`	`l.ori r5,r5,lo(0x44556677)`
`l.sw (PAGE_SIZE - 4)(r3),r5`	`l.sw (PAGE_SIZE - 4)(r3),r5`

`l.jal _dc_enable`	`l.jal dc_enable`
`l.nop`	`l.nop`

`/* I want this part to execute as fast as possible */`	`/* I want this part to execute as fast as possible */`
`l.jal _ic_enable`	`l.jal ic_enable`
`l.nop`	`l.nop`

`l.addi r5,r3,PAGE_SIZE`	`l.addi r5,r3,PAGE_SIZE`

`/* This jump is just to be shure that the following`	`/* This jump is just to be shure that the following`
Line 368...	Line 368...
`l.lwz r5,0(r3)`	`l.lwz r5,0(r3)`
`l.sfeq r6,r5`	`l.sfeq r6,r5`
`l.bnf 19f`	`l.bnf 19f`
`l.nop`	`l.nop`

`l.jal _dc_disable`	`l.jal dc_disable`
`l.nop`	`l.nop`

`l.jal _lo_dmmu_dis`	`l.jal lo_dmmu_dis`
`l.nop`	`l.nop`

`l.j 10f`	`l.j 10f`
`l.nop`	`l.nop`

Line 387...	Line 387...
`14: l.addi r8,r8,1`	`14: l.addi r8,r8,1`
`13: l.addi r8,r8,1`	`13: l.addi r8,r8,1`
`12: l.addi r8,r8,1`	`12: l.addi r8,r8,1`
`11: l.addi r8,r8,1`	`11: l.addi r8,r8,1`

`10: l.jal _dc_disable`	`10: l.jal dc_disable`
`l.nop`	`l.nop`

`l.jal _ic_disable`	`l.jal ic_disable`
`l.nop`	`l.nop`

`l.jal _lo_dmmu_dis`	`l.jal lo_dmmu_dis`
`l.nop`	`l.nop`

`l.addi r11,r8,0`	`l.addi r11,r8,0`
`l.sw 0(r0),r8`	`l.sw 0(r0),r8`
`l.sw 4(r0),r5`	`l.sw 4(r0),r5`
Line 405...	Line 405...
`l.lwz r9,0(r1)`	`l.lwz r9,0(r1)`
`l.jr r9`	`l.jr r9`
`l.addi r1,r1,4`	`l.addi r1,r1,4`

`/* itlb_ic_test(unsigned long add, unsigned long set) */`	`/* itlb_ic_test(unsigned long add, unsigned long set) */`
`_lo_itlb_ci_test:`	`lo_itlb_ci_test:`
`l.addi r1,r1,-4`	`l.addi r1,r1,-4`
`l.sw 0(r1),r9`	`l.sw 0(r1),r9`

`l.addi r8,r0,0`	`l.addi r8,r0,0`

`/* Copy the code to the prepeared location */`	`/* Copy the code to the prepeared location */`
`l.addi r7,r0,88`	`l.addi r7,r0,88`
`l.movhi r5,hi(_ci_test)`	`l.movhi r5,hi(ci_test)`
`l.ori r5,r5,lo(_ci_test)`	`l.ori r5,r5,lo(ci_test)`
`l.addi r6,r3,0`	`l.addi r6,r3,0`
`1: l.lwz r11,0(r5)`	`1: l.lwz r11,0(r5)`
`l.sw 0(r6),r11`	`l.sw 0(r6),r11`
`l.addi r5,r5,4`	`l.addi r5,r5,4`
`l.addi r6,r6,4`	`l.addi r6,r6,4`
Line 431...	Line 431...
`l.mtspr r4,r5,SPR_ITLBMR_BASE(0)`	`l.mtspr r4,r5,SPR_ITLBMR_BASE(0)`

`l.ori r5,r3,ITLB_PR_NOLIMIT`	`l.ori r5,r3,ITLB_PR_NOLIMIT`
`l.mtspr r4,r5,SPR_ITLBTR_BASE(0)`	`l.mtspr r4,r5,SPR_ITLBTR_BASE(0)`

`l.jal _lo_immu_en`	`l.jal lo_immu_en`
`l.nop`	`l.nop`
`l.jal _ic_enable`	`l.jal ic_enable`
`l.nop`	`l.nop`

`l.addi r5,r0,0`	`l.addi r5,r0,0`
`l.addi r6,r0,0`	`l.addi r6,r0,0`
`l.jalr r3`	`l.jalr r3`
Line 447...	Line 447...
`l.bnf 11f`	`l.bnf 11f`
`l.nop`	`l.nop`

`/* Copy the code to the prepeared location */`	`/* Copy the code to the prepeared location */`
`l.addi r7,r0,20`	`l.addi r7,r0,20`
`l.movhi r5,hi(_ic_refill_test)`	`l.movhi r5,hi(ic_refill_test)`
`l.ori r5,r5,lo(_ic_refill_test)`	`l.ori r5,r5,lo(ic_refill_test)`
`l.addi r6,r3,12`	`l.addi r6,r3,12`
`1: l.lwz r11,0(r5)`	`1: l.lwz r11,0(r5)`
`l.sw 0(r6),r11`	`l.sw 0(r6),r11`
`l.addi r5,r5,4`	`l.addi r5,r5,4`
`l.addi r6,r6,4`	`l.addi r6,r6,4`
`l.addi r7,r7,-4`	`l.addi r7,r7,-4`
`l.sfeqi r7,0`	`l.sfeqi r7,0`
`l.bnf 1b`	`l.bnf 1b`
`l.nop`	`l.nop`

`l.jal _ic_disable`	`l.jal ic_disable`
`l.nop`	`l.nop`
`l.jal _ic_enable`	`l.jal ic_enable`
`l.nop`	`l.nop`

`l.addi r5,r0,0`	`l.addi r5,r0,0`
`l.addi r6,r3,12`	`l.addi r6,r3,12`
`l.jalr r6`	`l.jalr r6`
Line 482...	Line 482...
`l.nop`	`l.nop`

`12: l.addi r8,r8,1`	`12: l.addi r8,r8,1`
`11: l.addi r8,r8,1`	`11: l.addi r8,r8,1`

`10: l.jal _ic_disable`	`10: l.jal ic_disable`
`l.nop`	`l.nop`

`l.jal _lo_dmmu_dis`	`l.jal lo_dmmu_dis`
`l.nop`	`l.nop`

`l.addi r11,r8,0`	`l.addi r11,r8,0`
`l.sw 0(r0),r11`	`l.sw 0(r0),r11`
`l.sw 4(r0),r5`	`l.sw 4(r0),r5`

`l.lwz r9,0(r1)`	`l.lwz r9,0(r1)`
`l.jr r9`	`l.jr r9`
`l.addi r1,r1,4`	`l.addi r1,r1,4`

`_ci_test:`	`ci_test:`
`3: l.addi r5,r5,1`	`3: l.addi r5,r5,1`

`l.sfeqi r6,0x01`	`l.sfeqi r6,0x01`
`l.bnf 1f`	`l.bnf 1f`
`l.nop`	`l.nop`
Line 527...	Line 527...

`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`


`_ic_refill_test:`	`ic_refill_test:`
`l.jr r9`	`l.jr r9`
`l.addi r5,r5,1`	`l.addi r5,r5,1`
`l.addi r5,r5,1`	`l.addi r5,r5,1`
`l.jr r9`	`l.jr r9`
`l.addi r5,r5,1`	`l.addi r5,r5,1`

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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mmu/] [mmu-asm.S] - Diff between revs 90 and 346