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/* ipc.h. Microkernel IPC header for Or1ksim
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/* spr-defs.h - Special purpose registers definitions file
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Copyright (C) 2000 Damjan Lampret
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Copyright (C) 2000 Damjan Lampret
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Copyright (C) 2008, 2010 Embecosm Limited
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Copyright (C) 2008, 2010 Embecosm Limited
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Contributor Damjan Lampret <lampret@opencores.org>
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Contributor Damjan Lampret <lampret@opencores.org>
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
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#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
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/* Data MMU group */
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/* Data MMU group */
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
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#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
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#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
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#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
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/* Instruction MMU group */
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/* Instruction MMU group */
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#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
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#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
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#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
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#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
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#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
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#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
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#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
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#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
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#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
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#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
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/* Power management group */
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/* Power management group */
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#define SPR_PMR (SPRGROUP_PM + 0)
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#define SPR_PMR (SPRGROUP_PM + 0)
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/* PIC group */
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/* PIC group */
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#define SPR_PICMR (SPRGROUP_PIC + 0)
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#define SPR_PICMR (SPRGROUP_PIC + 0)
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#define SPR_PICPR (SPRGROUP_PIC + 1)
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#define SPR_PICSR (SPRGROUP_PIC + 2)
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#define SPR_PICSR (SPRGROUP_PIC + 2)
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/* Tick Timer group */
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/* Tick Timer group */
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#define SPR_TTMR (SPRGROUP_TT + 0)
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#define SPR_TTMR (SPRGROUP_TT + 0)
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#define SPR_TTCR (SPRGROUP_TT + 1)
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#define SPR_TTCR (SPRGROUP_TT + 1)
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*/
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*/
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_V 0x00000001 /* Valid */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
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#define SPR_DTLBMR_VPN 0xffffe000 /* Virtual Page Number */
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/*
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/*
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* Bit definitions for the Data TLB Translate Register
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* Bit definitions for the Data TLB Translate Register
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*
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*
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*/
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*/
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#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_D 0x00000020 /* Dirty */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
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#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_DTLBTR_PPN 0xffffe000 /* Physical Page Number */
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/*
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/*
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* Bit definitions for the Instruction TLB Match Register
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* Bit definitions for the Instruction TLB Match Register
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*
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*
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*/
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*/
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_V 0x00000001 /* Valid */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
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#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
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#define SPR_ITLBMR_VPN 0xffffe000 /* Virtual Page Number */
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/*
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/*
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* Bit definitions for the Instruction TLB Translate Register
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* Bit definitions for the Instruction TLB Translate Register
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*
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*
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*/
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*/
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_A 0x00000010 /* Accessed */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_D 0x00000020 /* Dirty */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
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#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
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#define SPR_ITLBTR_PPN 0xffffe000 /* Physical Page Number */
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/*
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/*
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* Bit definitions for Data Cache Control register
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* Bit definitions for Data Cache Control register
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*
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*
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*/
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*/
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*
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*
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*/
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*/
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#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
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#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
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/*
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/*
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* Bit definitions for PICPR
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*
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*/
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#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
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/*
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* Bit definitions for PICSR
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* Bit definitions for PICSR
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*
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*
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*/
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*/
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#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
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#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
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/*
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/*
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* Bit definitions for Tick Timer Control Register
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* Bit definitions for Tick Timer Control Register
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*
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*
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*/
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*/
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#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */
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#define SPR_TTCR_CNT 0xffffffff /* Count, time period */
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#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
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#define SPR_TTMR_TP 0x0fffffff /* Time period */
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
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#define SPR_TTMR_DI 0x00000000 /* Disabled */
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#define SPR_TTMR_DI 0x00000000 /* Disabled */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_RT 0x40000000 /* Restart tick */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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