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/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
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/* ipc.h. Microkernel IPC header for Or1ksim
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Copyright (C) 2000 Damjan Lampret
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Copyright (C) 2008, 2010 Embecosm Limited
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Contributor Damjan Lampret <lampret@opencores.org>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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/* This file is part of test microkernel for OpenRISC 1000. */
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/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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/* Definition of special-purpose registers (SPRs). This is just a copy of
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#ifndef SPR_DEFS__H
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cpu/or1k/spr_defs.h. It really should not be duplicated here. */
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#define SPR_DEFS__H
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/* Definition of special-purpose registers (SPRs). */
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#define MAX_GRPS (32)
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#define MAX_GRPS (32)
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#define MAX_SPRS_PER_GRP_BITS (11)
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#define MAX_SPRS_PER_GRP_BITS (11)
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#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
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#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
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#define MAX_SPRS (0x10000)
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#define MAX_SPRS (0x10000)
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#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
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#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS)
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/* System control and status group */
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_UPR (SPRGROUP_SYS + 1)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_DCFGR (SPRGROUP_SYS + 7)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_PCCFGR (SPRGROUP_SYS + 8)
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
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#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
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#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
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/* Data MMU group */
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/* Data MMU group */
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
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/*
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/*
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* Bit definitions for the Version Register
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* Bit definitions for the Version Register
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*
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*
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*/
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*/
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_VER 0xff000000 /* Processor version */
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#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
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#define SPR_VR_RES 0x00ff0000 /* Reserved */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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#define SPR_VR_VER_OFF 24
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#define SPR_VR_CFG_OFF 16
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#define SPR_VR_REV_OFF 0
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/*
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/*
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* Bit definitions for the Unit Present Register
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* Bit definitions for the Unit Present Register
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*
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*
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*/
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*/
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#define SPR_UPR_UP 0x00000001 /* UPR present */
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#define SPR_UPR_UP 0x00000001 /* UPR present */
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#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
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#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
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#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
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#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
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#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
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#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
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#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
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#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
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#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
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#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
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#define SPR_DCFGR_WPCI 0x00000080 /* Watchpoint counters implemented */
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#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
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#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
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#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
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2 == n ? SPR_DCFGR_NDP2 : \
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2 == n ? SPR_DCFGR_NDP2 : \
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3 == n ? SPR_DCFGR_NDP3 : \
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3 == n ? SPR_DCFGR_NDP3 : \
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4 == n ? SPR_DCFGR_NDP4 : \
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4 == n ? SPR_DCFGR_NDP4 : \
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#define SPR_DCCFGR_CBPRI 0x00000800
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#define SPR_DCCFGR_CBPRI 0x00000800
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#define SPR_DCCFGR_CBLRI 0x00001000
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#define SPR_DCCFGR_CBLRI 0x00001000
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#define SPR_DCCFGR_CBFRI 0x00002000
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#define SPR_DCCFGR_CBFRI 0x00002000
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#define SPR_DCCFGR_CBWBRI 0x00004000
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#define SPR_DCCFGR_CBWBRI 0x00004000
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#define SPR_DCCFGR_NCW_OFF 0
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#define SPR_DCCFGR_NCS_OFF 3
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#define SPR_DCCFGR_CBS_OFF 7
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/*
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/*
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* Bit definitions for Instruction Cache Configuration Register
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* Bit definitions for Instruction Cache Configuration Register
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*
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*
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*/
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*/
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#define SPR_ICCFGR_NCW 0x00000007
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#define SPR_ICCFGR_NCW 0x00000007
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#define SPR_ICCFGR_CCRI 0x00000200
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#define SPR_ICCFGR_CCRI 0x00000200
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#define SPR_ICCFGR_CBIRI 0x00000400
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#define SPR_ICCFGR_CBIRI 0x00000400
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#define SPR_ICCFGR_CBPRI 0x00000800
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#define SPR_ICCFGR_CBPRI 0x00000800
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#define SPR_ICCFGR_CBLRI 0x00001000
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#define SPR_ICCFGR_CBLRI 0x00001000
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#define SPR_ICCFGR_NCW_OFF 0
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#define SPR_ICCFGR_NCS_OFF 3
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#define SPR_ICCFGR_CBS_OFF 7
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/*
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/*
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* Bit definitions for Data MMU Configuration Register
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* Bit definitions for Data MMU Configuration Register
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*
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*
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*/
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*/
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#define SPR_DMMUCFGR_CRI 0x00000100
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#define SPR_DMMUCFGR_CRI 0x00000100
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#define SPR_DMMUCFGR_PRI 0x00000200
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#define SPR_DMMUCFGR_PRI 0x00000200
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#define SPR_DMMUCFGR_TEIRI 0x00000400
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#define SPR_DMMUCFGR_TEIRI 0x00000400
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#define SPR_DMMUCFGR_HTR 0x00000800
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#define SPR_DMMUCFGR_HTR 0x00000800
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#define SPR_DMMUCFGR_NTW_OFF 0
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#define SPR_DMMUCFGR_NTS_OFF 2
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/*
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/*
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* Bit definitions for Instruction MMU Configuration Register
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* Bit definitions for Instruction MMU Configuration Register
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*
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*
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*/
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*/
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#define SPR_IMMUCFGR_CRI 0x00000100
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#define SPR_IMMUCFGR_CRI 0x00000100
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#define SPR_IMMUCFGR_PRI 0x00000200
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#define SPR_IMMUCFGR_PRI 0x00000200
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#define SPR_IMMUCFGR_TEIRI 0x00000400
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#define SPR_IMMUCFGR_TEIRI 0x00000400
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#define SPR_IMMUCFGR_HTR 0x00000800
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#define SPR_IMMUCFGR_HTR 0x00000800
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#define SPR_IMMUCFGR_NTW_OFF 0
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#define SPR_IMMUCFGR_NTS_OFF 2
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/*
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/*
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* Bit definitions for Debug Control registers
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* Bit definitions for Debug Control registers
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*
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*
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*/
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*/
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
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#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_RE 0x00000400 /* Range exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SCE 0x00000800 /* System call exception */
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#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */
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#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
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#define SPR_DSR_TE 0x00002000 /* Trap exception */
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#define SPR_DSR_TE 0x00002000 /* Trap exception */
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/*
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/*
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* Bit definitions for Debug reason register
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* Bit definitions for Debug reason register
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*
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*
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#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_RE 0x00000400 /* Range exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_SCE 0x00000800 /* System call exception */
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#define SPR_DRR_TE 0x00001000 /* Trap exception */
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#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
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#define SPR_DRR_TE 0x00002000 /* Trap exception */
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/*
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/*
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* Bit definitions for Performance counters mode registers
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* Bit definitions for Performance counters mode registers
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*
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*
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*/
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*/
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_SR 0x80000000 /* Single run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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#define SPR_TTMR_M 0xc0000000 /* Tick mode */
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/*
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/*
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* Bit definitions for the FP Control Status Register
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*
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*/
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#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
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#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
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#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
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#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
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#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
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#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
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#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
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#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
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#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
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#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
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#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
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#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
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SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
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SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
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#define FPCSR_RM_RN (0<<1)
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#define FPCSR_RM_RZ (1<<1)
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#define FPCSR_RM_RIP (2<<1)
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#define FPCSR_RM_RIN (3<<1)
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/*
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* l.nop constants
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* l.nop constants
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*
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*
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*/
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*/
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_NOP 0x0000 /* Normal nop instruction */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_EXIT 0x0001 /* End of simulation */
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#define NOP_REPORT 0x0002 /* Simple report */
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#define NOP_REPORT 0x0002 /* Simple report */
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/*#define NOP_PRINTF 0x0003 Simprintf instruction now obsolete */
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/*#define NOP_PRINTF 0x0003 Simprintf instruction (obsolete)*/
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#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */
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#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */
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#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
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#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
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#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */
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#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */
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#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */
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#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */
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#define NOP_REPORT_FIRST 0x0400 /* Report with number */
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#define NOP_REPORT_FIRST 0x0400 /* Report with number */
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#define NOP_REPORT_LAST 0x03ff /* Report with number */
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#define NOP_REPORT_LAST 0x03ff /* Report with number */
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#endif /* SPR_DEFS__H */
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