OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [spr-defs.h] - Diff between revs 385 and 432

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 385 Rev 432
Line 151... Line 151...
/* Power management group */
/* Power management group */
#define SPR_PMR (SPRGROUP_PM + 0)
#define SPR_PMR (SPRGROUP_PM + 0)
 
 
/* PIC group */
/* PIC group */
#define SPR_PICMR (SPRGROUP_PIC + 0)
#define SPR_PICMR (SPRGROUP_PIC + 0)
#define SPR_PICPR (SPRGROUP_PIC + 1)
 
#define SPR_PICSR (SPRGROUP_PIC + 2)
#define SPR_PICSR (SPRGROUP_PIC + 2)
 
 
/* Tick Timer group */
/* Tick Timer group */
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTCR (SPRGROUP_TT + 1)
#define SPR_TTCR (SPRGROUP_TT + 1)
Line 567... Line 566...
 *
 *
 */
 */
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
 
 
/*
/*
 * Bit definitions for PICPR
 
 *
 
 */
 
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
 
 
 
/*
 
 * Bit definitions for PICSR
 * Bit definitions for PICSR
 *
 *
 */
 */
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.