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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [spr-defs.h] - Diff between revs 483 and 538

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/* ipc.h.  Microkernel IPC header for Or1ksim
/* spr-defs.h - Special purpose registers definitions file
 
 
   Copyright (C) 2000 Damjan Lampret
   Copyright (C) 2000 Damjan Lampret
   Copyright (C) 2008, 2010 Embecosm Limited
   Copyright (C) 2008, 2010 Embecosm Limited
 
 
   Contributor Damjan Lampret <lampret@opencores.org>
   Contributor Damjan Lampret <lampret@opencores.org>
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#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
#define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
#define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
 
 
/* Data MMU group */
/* Data MMU group */
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
 
#define SPR_DTLBEIR     (SPRGROUP_DMMU + 2)
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
 
 
/* Instruction MMU group */
/* Instruction MMU group */
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
 
#define SPR_ITLBEIR     (SPRGROUP_IMMU + 2)
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
 
 
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/* Power management group */
/* Power management group */
#define SPR_PMR (SPRGROUP_PM + 0)
#define SPR_PMR (SPRGROUP_PM + 0)
 
 
/* PIC group */
/* PIC group */
#define SPR_PICMR (SPRGROUP_PIC + 0)
#define SPR_PICMR (SPRGROUP_PIC + 0)
 
#define SPR_PICPR (SPRGROUP_PIC + 1)
#define SPR_PICSR (SPRGROUP_PIC + 2)
#define SPR_PICSR (SPRGROUP_PIC + 2)
 
 
/* Tick Timer group */
/* Tick Timer group */
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTMR (SPRGROUP_TT + 0)
#define SPR_TTCR (SPRGROUP_TT + 1)
#define SPR_TTCR (SPRGROUP_TT + 1)
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 */
 */
#define SPR_DTLBMR_V       0x00000001  /* Valid */
#define SPR_DTLBMR_V       0x00000001  /* Valid */
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
#define SPR_DTLBMR_VPN     0xffffe000  /* Virtual Page Number */
 
 
/*
/*
 * Bit definitions for the Data TLB Translate Register
 * Bit definitions for the Data TLB Translate Register
 *
 *
 */
 */
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#define SPR_DTLBTR_D       0x00000020  /* Dirty */
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
#define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
#define SPR_DTLBTR_PPN     0xffffe000  /* Physical Page Number */
 
 
/*
/*
 * Bit definitions for the Instruction TLB Match Register
 * Bit definitions for the Instruction TLB Match Register
 *
 *
 */
 */
#define SPR_ITLBMR_V       0x00000001  /* Valid */
#define SPR_ITLBMR_V       0x00000001  /* Valid */
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
#define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
#define SPR_ITLBMR_VPN     0xffffe000  /* Virtual Page Number */
 
 
/*
/*
 * Bit definitions for the Instruction TLB Translate Register
 * Bit definitions for the Instruction TLB Translate Register
 *
 *
 */
 */
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#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
#define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
#define SPR_ITLBTR_PPN     0xffffe000  /* Physical Page Number */
 
 
/*
/*
 * Bit definitions for Data Cache Control register
 * Bit definitions for Data Cache Control register
 *
 *
 */
 */
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 *
 *
 */
 */
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
 
 
/*
/*
 
 * Bit definitions for PICPR
 
 *
 
 */
 
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
 
 
 
/*
 * Bit definitions for PICSR
 * Bit definitions for PICSR
 *
 *
 */
 */
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
 
 
/*
/*
 * Bit definitions for Tick Timer Control Register
 * Bit definitions for Tick Timer Control Register
 *
 *
 */
 */
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
#define SPR_TTCR_CNT    0xffffffff  /* Count, time period */
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
#define SPR_TTMR_TP     0x0fffffff  /* Time period */
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
#define SPR_TTMR_DI     0x00000000  /* Disabled */
#define SPR_TTMR_DI     0x00000000  /* Disabled */
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
#define SPR_TTMR_SR     0x80000000  /* Single run */
#define SPR_TTMR_SR     0x80000000  /* Single run */

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